M95128-RMB6GSLASHA datasheet(14/44 Pages) STMICROELECTRONICS

14 / 44 page

Instructions

M95128, M95128-W, M95128-R

14/44

Instructions

Each instruction starts with a single-byte code, as summarized in Table 3.

If an invalid instruction is sent (one not contained in Table 3), the device automatically

deselects itself.

5.1

Write Enable (WREN)

The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.

The only way to do this is to send a Write Enable instruction to the device.

As shown in Figure 5, to send this instruction to the device, Chip Select (S) is driven Low,

and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then

enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven

High.

Figure 5.

Write Enable (WREN) sequence

Table 3.

Instruction set

Instruction

Description

Instruction format

WREN

Write Enable

0000 0110

WRDI

Write Disable

0000 0100

RDSR

Read Status Register

0000 0101

WRSR

Write Status Register

0000 0001

READ

Read from Memory Array

0000 0011

WRITE

Write to Memory Array

0000 0010

AI02281E

34567

High Impedance

Instruction

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