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LTC1863IGN 数据表(PDF) 7 Page - Linear Technology |
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LTC1863IGN 数据表(HTML) 7 Page - Linear Technology |
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7 / 16 page ![]() LTC1863/LTC1867 7 18637f PI FU CTIO S CHO-CH7/COM (Pins 1-8): Analog Input Pins. Analog inputs must be free of noise with respect to GND. CH7/ COM can be either a separate channel or the common minus input for the other channels. REFCOMP (Pin 9): Reference Buffer Output Pin. Bypass to GND with 10 µF tantalum capacitor in parallel with 0.1µF ceramic capacitor (4.096V Nominal). To overdrive REFCOMP, tie VREF to GND. VREF (Pin 10): 2.5V Reference Output. This pin can also be used as an external reference buffer input for improved accuracy and drift. Bypass to GND with 2.2 µF tantalum capacitor in parallel with 0.1 µF ceramic capacitor. CS/CONV (Pin 11): This input provides the dual function of initiating conversions on the ADC and also frames the serial data transfer. SCK (Pin 12): Shift Clock. This clock synchronizes the serial data transfer. SDO (Pin 13): Digital Data Output. The A/D conversion result is shifted out of this output. Straight binary format for unipolar mode and two’s complement format for bipolar mode. SDI (Pin 14): Digital Data Input Pin. The A/D configuration word is shifted into this input. GND (Pin 15): Analog and Digital GND. VDD (Pin 16): Analog and Digital Power Supply. Bypass to GND with 10 µF tantalum capacitor in parallel with 0.1µF ceramic capacitor. TEST CIRCUITS TYPICAL CO ECTIO DIAGRA CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7/COM VDD GND SDI SDO SCK CS/CONV VREF REFCOMP LTC1863/ LTC1867 – + + DIGITAL I/O 5V 4.096V 10 µF 2.2 µF 2.5V ±2.048V DIFFERENTIAL INPUTS 4.096V SINGLE-ENDED INPUT 18637 TCD 3k (A) Hi-Z TO VOH AND VOL TO VOH CL 3k 5V DN DN (B) Hi-Z TO VOL AND VOH TO VOL CL 18637 TC01 3k (A) VOH TO Hi-Z CL 3k 5V DN DN (B) VOL TO Hi-Z CL 18637 TC02 Load Circuits for Access Timing Load Circuits for Output Float Delay |
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