Data Sheet

ADPL42001

analog.com

Rev. 0

4 of 17

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

ADPL42001

+

2

3

4

5

6

*EP

TDFN

TSOT

TOP VIEW

ADPL42001

IN

1

2

GND

EN

3

6

5

4

+

OUT

FB

PGOOD

TOP VIEW

1

Pin Descriptions

Table 3. Pin Descriptions

PIN

NAME

DESCRIPTION

TSOT

TDFN

1

2

EN

Active-High, Enable Input. Force EN high (or connect to IN) to turn the

regulator on. Pull EN to GND to place the device in a low-power shutdown

mode.

2

3

GND

Ground. Connect GND to the ground plane.

3

1

IN

Power-Supply Input. Decouple to GND with a 0.1µF capacitor; place the

capacitor close to the IN and GND pins.

4

6

OUT

Regulator Output. Connect at least 4.7µF, 0805 capacitor from OUT to GND.

5

5

PGOOD

Open-Drain PGOOD Output. Pull up PGOOD to an external power supply.

PGOOD pulls low if FB drops below 89% of its set value. PGOOD goes high

after FB rises above 92% of its set value. The PGOOD pin can be left floating if

not used.

6

4

FB

Output Feedback Connection. Connect FB to a resistor divider between VOUT

and GND to adjust the output voltage from 0.6V to 18V.

—

—

EP

Exposed Pad (TDFN Only). Always connect EP to the GND pin of the IC.

Connect EP to a large GND plane with several thermal vias for best thermal

performance. Refer to the ADPL42001ATT EV kit user guide for an example of

the correct method for EP connection and thermal vias.