ST1S10 datasheet(9/26 Pages) STMICROELECTRONICS

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ST1S10

Application information

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duty cycle (at VIN_min) should be considered in order to determine the max IRMS flowing

through the input capacitor.

A minimum value of 4.7 µF for the VIN_SW and a 0.1 µF ceramic capacitor for the VIN_A are

suitable in most application conditions. A 10 µF or higher ceramic capacitor for the VIN_SW

and a 1 µF or higher for the VIN_A are recommended in cases of higher power supply source

impedance or where long wires are needed between the power supply source and the VIN

pins. The above higher input capacitor values are also recommended in cases where an

output capacitive load is present (47 µF < CLOAD < 100 µF), which could impact the

switching peak current drawn from the input capacitor during the start-up transient.

In cases of very high output capacitive loads (CLOAD > 100 µF), all input/output capacitor

values shall be modified as described in the OCP and SCP operation section 5.8.5 of this

document.

The input ceramic capacitors should have a voltage rating in the range of 1.5 times the

maximum input voltage and be located as close as possible to VIN pins.

5.3

Output capacitor (VOUT > 2.5 V)

The most important parameters for the output capacitor are the capacitance, the ESR and

the voltage rating. The capacitance and the ESR affect the control loop stability, the output

ripple voltage and transient response of the regulator.

The ripple due to the capacitance can be calculated with the following formula:

VRIPPLE(C) = (0.125 x ΔISW) / (FS x COUT)

where FS is the PWM switching frequency and ΔISW is the inductor peak-to-peak switching

current, which can be calculated as:

ΔISW = [(VIN - VOUT) / (FS x L)] x D

where D is the duty cycle.

The ripple due to the ESR is given by:

VRIPPLE(ESR) = ΔISW x ESR

The equations above can be used to define the capacitor selection range, but final values

should be verified by testing an evaluation circuit.

Lower ESR ceramic capacitors are usually recommended to reduce the output ripple

voltage. Capacitors with higher voltage ratings have lower ESR values, resulting in lower

output ripple voltage.

Also, the capacitor ESL value impacts the output ripple voltage, but ceramic capacitors

usually have very low ESL, making ripple voltages due to the ESL negligible. In order to

reduce ripple voltages due to the parasitic inductive effect, the output capacitor connection

paths should be kept as short as possible.

The ST1S10 has been designed to perform best with ceramic capacitors. Under typical

application conditions a minimum ceramic capacitor value of 22 µF is recommended on the

output, but higher values are suitable considering that the control loop has been designed to

work properly with a natural output LC frequency provided by a 3.3 µH inductor and 22 µF

output capacitor. If the high capacitive load application circuit shown in Figure 3 is used, a

47 µF (or 2 x 22 µF capacitors in parallel) could be needed as described in the OCP and

SCP operation section 5.8.5. of this document.

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