STW81101AT datasheet(23/48 Pages) STMICROELECTRONICS

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STW81101

Circuit description

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The SERCAL bit should be set to 1 at each division ratio change. Note that to reset the auto

calibrator state machine after a power-up, and before the first calibration in any case, the

INITCAL bit should be set to 1 and back to 0 (the Power On Reset circuitry does this

automatically). The calibration requires approximately 7 periods of the PFD frequency.

The maximum allowed FPFD to perform the calibration process is 1 MHz. When using a

higher FPFD , follow the steps below:

Calibrate the VCO at the desired frequency with an FPFD less than 1 MHz.

Set the A, B and R dividers ratio for the desired FPFD .

5.8.3

VCO voltage amplitude control

The voltage swing of the VCOs can be adjusted over four levels by means of two dedicated

programming bits (PLL_A1 and PLL_A0). This setting trades current consumption with

phase noise performances of the VCO. Higher amplitudes provide best phase noise,

whereas lower amplitudes save power.

Table 8 gives the voltage swing level expected on the resonator nodes, the current

consumption, and the phase noise @1MHz.

Table 8.

VCO A performances versus amplitude setting (Freq=3.6GHz)

PLL_A[1:0]

Differential

voltage swing (Vp)

Current

consumption (mA)

PN @1MHz (dBc/Hz)

1.1

-124

1.3

-125

1.9

-128.5

2.1

-129

Table 9.

VCO B performances vs. amplitude setting (Freq=4.1GHz)

PLL_A[1:0]

Differential

voltage swing (Vp)

Current

consumption (mA)

PN @1MHz (dBc/Hz)

1.1

-123

1.3

-125

1.9

-127.5

2.1

-128

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