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CLK

t

CPW

t

CLK

t

CPW

t

SD

t

S

t

DIST

t

DOHD

t

SPW

Bit15(MSB)

Bit14

Bit13

t

SPW

t

DOPD

t

CD

t

DS

t

MSBPD

t

DIHD

· · ·

t

CONV

DRDY

SCLK

DOUT

DIN

TIMING REQUIREMENTS: SPI FORMAT

ADS1174

ADS1178

SBAS373 – OCTOBER 2007

TIMING CHARACTERISTICS: SPI FORMAT

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

37

10,000

ns

CLK positive or negative pulse width

15

ns

(1)

256

2560

CLK periods

(2)

Falling edge of CLK to falling edge of DRDY

22

ns

(2)

Falling edge of DRDY to rising edge of first SCLK to retrieve data

1

CLK period

DRDY falling edge to DOUT MSB valid (propagation delay)

12

ns

(2)

Falling edge of SCLK to rising edge of DRDY

18

ns

(3)

SCLK period

ns

SCLK positive or negative pulse width

ns

(2) (4)

SCLK falling edge to new DOUT invalid (hold time)

10

ns

(2)

SCLK falling edge to new DOUT valid (propagation delay)

31

ns

New DIN valid to falling edge of SCLK (setup time)

6

ns

(4)

Old DIN valid to falling edge of SCLK (hold time)

6

ns

(1)

(2)

Load on DRDY and DOUT = 20pF.

(3)

(4)

ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is 4ns.

Copyright © 2007, Texas Instruments Incorporated

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