M95M01-RMW6TG datasheet(12/39 Pages) STMICROELECTRONICS

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Operating features

M95M01-R

12/39

Operating features

4.1

Supply voltage (VCC)

4.1.1

Operating supply voltage VCC

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage

within the specified [VCC(min), VCC(max)] range must be applied (see Table 8.). In order to

secure a stable DC supply voltage, it is recommended to decouple the VCC line with a

suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package

pins.

This voltage must remain stable and valid until the end of the transmission of the instruction

and, for a Write instruction, until the completion of the internal write cycle (tW).

4.1.2

Power-up conditions

When the power supply is turned on, VCC rises continuously from VSS to VCC. During this

time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage, it is

therefore recommended to connect the S line to VCC via a suitable pull-up resistor.

In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge

sensitive as well as level sensitive: after power-up, the device does not become selected

until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select

(S) must have been High, prior to going Low to start the first operation.

The VCC rise time must not vary faster than 1 V/µs.

4.1.3

Device reset

In order to prevent inadvertent Write operations during power-up (continuous rise of VCC), a

power on reset (POR) circuit is included. At Power-up, the device does not respond to any

instruction until VCC has reached the power on reset threshold voltage (this threshold is

lower than the minimum VCC operating voltage defined in Table 8).

When VCC has passed the POR threshold, the device is reset and in the following state:

●

Standby Power mode

●

deselected (at next Power-up, a falling edge is required on Chip Select (S) before any

instructions can be started)

●

not in the Hold condition

●

Status Register:

–

the Write Enable Latch (WEL) is reset to 0

–

Write In Progress (WIP) is reset to 0. The SRWD, BP1 and BP0 bits of the Status

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