s

Independent 16 Qword (128 byte) read

and 32 Qword (256 byte) write FIFOs

s

Deferred reads, deferred writes, posted

writes, read ahead, and programmable read

prefetch counter

s

Programmable #READY time out

and recovery

Advanced Performance Features Common to

DMA, Direct Master, and Direct Slave

s

Zero wait state PCI & local bus bursts

s

Deep FIFOs prolong bursts

s

Unaligned PCI and local bus transfers of

any byte length

s

On-the-fly Endian conversion

s

Programmable local bus wait states

s

Parity checking on both buses

Messaging

s

Provides industry standard I2O r1.5

messaging unit

s

Supports general-purpose messaging

for proprietary message schemes

environments

driven environments

Embedded Host Features

s

PCI arbiter supports 7 external masters

s

Reset and interrupt signals configurable for

embedded host operation

s

Type 0/1 Configuration support allows

local bus master to configure PCI bus

and devices

Package

s

272-pin PBGA

Backward Compatibility

s

The PCI 9656 register set is backward

compatible with the PCI 9054, with new

registers added for the new functionality

enhancements

Related PLX Products

s

Support for 32-bit, 66MHz PCI with 32-bit,

66MHz C, J, and M Local Bus support is

provided by the PCI 9056

Serial EEPROM

s

Store configuration register power on,

reset values

s

An alternative to expansion ROM for stor-

ing Vital Product Data (VPD)

s

Supports 2 Kbit/4 Kbit microwire devices

with sequential read

Data Pipe Architecture

DMA

Service DMA descriptors, mastering on both

bus interfaces during data transfer

s

Two independent channels provide flexible

prioritization scheme

s

Each channel has its own bi-directional

32 Qword (256 byte) deep FIFO

s

Block Mode services a single DMA

descriptor in PCI 9656 registers

s

Scatter/Gather Mode services DMA

descriptor linked lists in memory

bus memory

circular (dynamic) with Valid bit sema-

phore control

s

Direct Hardware DMA controls

s

Programmable local bus burst length,

including infinite

PowerQUICC 16 byte limit

Direct Master

Service local bus masters by mastering on

the PCI bus

s

Two local bus address spaces map to PCI

bus: one to memory; one to I/O

s

Generate all PCI memory and I/O

transaction types, including Memory

Write and Invalidate (MWI)

s

Independent 16 Qword (128 byte) read

and 32 Qword (256 byte) write FIFOs

s

Read ahead and programmable read

prefetch counter

s

PowerQUICC deferred reads and IDMA

(M mode only)

Direct Slave

Service PCI bus masters by mastering on the

local bus

s

Two general-purpose and one expansion

ROM PCI address spaces map to local

bus memory

or 32-bit local bus data transfer

PCI 9656 Features

The PCI 9656 64-bit, 66MHz PCI I/O accelera-

tor is the most advanced, general-purpose

bus mastering device available for Motorola

MPC 850/860 PowerQUICC and generic

32-bit, 66MHz local bus based designs. The

PCI 9656 incorporates PLX’s industry leading

Data Pipe Architecture technology, featuring

DMA engines, programmable Direct Master

and Direct Slave data transfer modes, and PCI

messaging functions.

Interfaces

PCI

s

64-bit, 66MHz r2.2 operation

PCI bus master

s

PICMG 2.1 r2.0 Hot Swap Silicon

s

PCI Hot Plug r1.0

s

PCI Power Management r1.1

power states

generation to meet PC 2001 Windows

98/2000 communication adapter logo

certification requirements

Local Bus

s

Three local bus options on the device

PowerQUICC and PowerPC 80x/82x

and FPGAs, and others

buses for Intel i960, IBM PowerPC 401, IDT

RC32364, DSPs, IOP 480, and others

s

32-bit, 66MHz operation

and local bus