LPC2132FBD64SLASH01 datasheet(24/39 Pages) NXP

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LPC2131_32_34_36_38_4

Product data sheet

Rev. 04 — 16 October 2007

24 of 39

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

6.18.8 Power Control

The LPC2131/32/34/36/38 support two reduced power modes: Idle mode and

Power-down mode.

In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs.

Peripheral functions continue operation during Idle mode and may generate interrupts to

cause the processor to resume execution. Idle mode eliminates power used by the

processor itself, memory systems and related controllers, and internal buses.

In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.

The processor state and registers, peripheral registers, and internal SRAM values are

preserved throughout Power-down mode and the logic levels of chip output pins remain

static. The Power-down mode can be terminated and normal operation resumed by either

a reset or certain speciﬁc interrupts that are able to function without clocks. Since all

dynamic operation of the chip is suspended, Power-down mode reduces chip power

consumption to nearly zero.

Selecting an external 32 kHz clock instead of the PCLK as a clock-source for the on-chip

RTC will enable the microcontroller to have the RTC active during Power-down mode.

Power-down current is increased with RTC active. However, it is signiﬁcantly lower than in

Idle mode.

A Power Control for Peripherals feature allows individual peripherals to be turned off if

they are not needed in the application, resulting in additional power savings.

6.18.9 VPB bus

The VPB divider determines the relationship between the processor clock (CCLK) and the

clock used by peripheral devices (PCLK). The VPB divider serves two purposes. The ﬁrst

is to provide peripherals with the desired PCLK via VPB bus so that they can operate at

the speed chosen for the ARM processor. In order to achieve this, the VPB bus may be

slowed down to 1

⁄

2 to

⁄

4 of the processor clock rate. Because the VPB bus must work

properly at power-up (and its timing cannot be altered if it does not work since the VPB

divider control registers reside on the VPB bus), the default condition at reset is for the

VPB bus to run at 1

⁄

4 of the processor clock rate. The second purpose of the VPB divider

is to allow power savings when an application does not require any peripherals to run at

the full processor rate. Because the VPB divider is connected to the PLL output, the PLL

remains active (if it was running) during Idle mode.

6.19 Emulation and debugging

The LPC2131/32/34/36/38 support emulation and debugging via a JTAG serial port. A

trace port allows tracing program execution. Debugging and trace functions are

multiplexed only with GPIOs on Port 1. This means that all communication, timer and

interface peripherals residing on Port 0 are available during the development and

debugging phase as they are when the application is run in the embedded system itself.

6.19.1 EmbeddedICE

Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of

the target system requires a host computer running the debugger software and an

EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the Remote

Debug Protocol commands to the JTAG data needed to access the ARM core.

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