74ALVC573_3

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 03 — 26 October 2007

5 of 17

NXP Semiconductors

74ALVC573

Octal D-type transparent latch; 3-state

6.

Functional description

[1]

H = HIGH voltage level

h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition

L = LOW voltage level

l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition

Z = High-impedance OFF-state

7.

Limiting values

[1]

The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2]

[3]

For SO20 packages: above 70

°C derate linearly with 8 mW/K.

For TSSOP20 packages: above 60

°C derate linearly with 5.5 mW/K.

For DHVQFN20 packages: above 60

°C derate linearly with 4.5 mW/K.

Table 3.

Functional table[1]

Operating modes

Input

Internal latch

Output

OE

LE

Dn

Qn

Enable and read register

(transparent mode)

LH

LLL

L

HHHH

Latch and read register

L

L

l

L

L

LLhH

H

Latch register and disable

outputs

HL

l

L

Z

H

LhH

Z

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Max

Unit

supply voltage

−0.5

+4.6

V

input clamping current

−50

-

mA

input voltage

−0.5

+4.6

V

output clamping current

-

±50

mA

output voltage

output HIGH or LOW state

[1] [2]

−0.5

V

output 3-state

−0.5

+4.6

V

[2]

−0.5

+4.6

V

output current

-

±50

mA

supply current

-

100

mA

ground current

−100

-

mA

storage temperature

−65

+150

°C

total power dissipation

[3]

-

500

mW