TMS320C6421 datasheet(2/223 Pages) TI

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1.2 Description

TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346C – JANUARY 2007 – REVISED NOVEMBER 2007

• Packages:

–

361-Pin Pb-Free PBGA Package

• VLYNQ™ Interface (FPGA Interface)

(ZWT Suffix), 0.8-mm Ball Pitch

• Three Pulse Width Modulator (PWM) Outputs

–

376-Pin Plastic BGA Package

• On-Chip ROM Bootloader

(ZDU Suffix), 1.0-mm Ball Pitch

• Individual Power-Savings Modes

• 0.09-µm/6-Level Cu Metal Process (CMOS)

• Flexible PLL Clock Generators

• 3.3-V and 1.8-V I/O, 1.2-V Internal

• IEEE-1149.1 (JTAG™)

(-6/-5/-5Q/-5S/-4/-4Q/-4S)

Boundary-Scan-Compatible

• 3.3-V and 1.8-V I/O, 1.05-V Internal

• Up to 111 General-Purpose I/O (GPIO) Pins

(-6 when SYSCLK1

≤ 400 MHz only)

(Multiplexed With Other Device Functions)

• Applications:

–

Telecom

–

Audio

–

Industrial Applications

The TMS320C64x+™ DSPs (including the TMS320C6421 device) are the highest-performance fixed-point

DSP generation in the TMS320C6000™ DSP platform. The C6421 device is based on the third-generation

high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by

Texas Instruments (TI), making these DSPs an excellent choice for digital signal processor applications.

The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™

DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from

previous devices.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and

C64x+ CPU, respectively.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the

C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses

the operational flexibility of high-speed controllers and the numerical capability of array processors. The

C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly

independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The

eight functional units include instructions to accelerate the performance in telecom, audio, and industrial

applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of

2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For

more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference

Guide (literature number SPRU732).

The C6421 also has application-specific hardware logic, on-chip memory, and additional on-chip

peripherals similar to the other C6000 DSP platform devices. The C6421 core uses a two-level

cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 128K-bit memory

space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D)

consists of a 384K-bit memory space that can be configured as mapped memory or 2-way set-associative

cache. The Level 2 memory/cache (L2) consists of a 512K-bit memory space that is shared between

program and data space. L2 memory can be configured as mapped memory, cache, or combinations of

the two.

TMS320C6421 Fixed-Point Digital Signal Processor

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