DAC8564IAPWR datasheet(27/46 Pages) TI

27 / 46 page

www.ti.com

SERIAL INTERFACE

IOVDD AND VOLTAGE TRANSLATORS

INPUT SHIFT REGISTER

DAC8564

SBAS403A – JUNE 2007 – REVISED NOVEMBER 2007

The DAC8564 has a 3-wire serial interface (SYNC,

The IOVDD pin powers the the digital input structures

SCLK, and DIN) compatible with SPI, QSPI, and

of the DAC8564. For single-supply operation, it can

Microwire interface standards, as well as most DSPs.

be tied to AVDD. For dual-supply operation, the IOVDD

See the Serial Write Operation timing diagram for an

pin provides interface flexibility with various CMOS

example of a typical write sequence.

logic families and should be connected to the logic

supply of the system. Analog circuits and internal

The write sequence begins by bringing the SYNC line

logic of the DAC8564 use AVDD as the supply

low. Data from the DIN line are clocked into the 24-bit

voltage. The external logic high inputs translate to

shift register on each falling edge of SCLK. The serial

AVDD by level shifters. These level shifters use the

clock frequency can be as high as 50MHz, making

IOVDD voltage as a reference to shift the incoming

the DAC8564 compatible with high-speed DSPs. On

logic HIGH levels to AVDD. IOVDD is ensured to

the 24th falling edge of the serial clock, the last data

operate from 2.7V to 5.5V regardless of the AVDD

bit is clocked into the shift register and the shift

voltage, assuring compatibility with various logic

families. Although specified down to 2.7V, IOVDD

shift register data. Once 24 bits are locked into the

operates at as low as 1.8V with degraded timing and

shift register, the eight MSBs are used as control bits

temperature

performance.

For

lowest

power

and the 16 LSBs are used as data. After receiving the

consumption, logic VIH levels should be as close as

24th falling clock edge, the DAC8564 decodes the

possible to IOVDD, and logic VIL levels should be as

eight control bits and 16 data bits to perform the

close as possible to GND voltages.

required function, without waiting for a SYNC rising

edge. A new write sequence starts at the next falling

edge of SYNC. A rising edge of SYNC before the

24-bit sequence is complete resets the SPI interface;

The input shift register (SR) of the DAC8564 is 24

no data transfer occurs. After the 24th falling edge of

bits wide, as shown in Table 4, and consists of eight

SCLK is received, the SYNC line may be kept LOW

control bits (DB23 and DB22) and 16 data bits (DB15

or brought HIGH. In either case, the minimum delay

to DB0). The first two control bits (DB23 and DB22)

time from the 24th falling SCLK edge to the next

are the address match bits. The DAC8564 offers

falling SYNC edge must be met in order to properly

hardware-enabled addressing capability, allowing a

begin the next cycle. To assure the lowest power

single host to talk to up to four DAC8564s through a

consumption of the device, care should be taken that

single SPI bus without any glue logic, enabling up to

the levels are as close to each rail as possible. (Refer

16-channel operation. The state of DB23 should

to the Typical Characteristics section for Figure 36,

match the state of pin A1; similarly, the state of DB22

Figure 57, and Figure 79 (Supply Current vs Logic

should match the state of pin A0. If there is no match,

Input Voltage).

the control command and the data (DB21...DB0) are

ignored by the DAC8564. That is, if there is no

match, the DAC8564 is not addressed. Address

matching can be overridden by the broadcast update.

Table 4. Data Input Register Format

DB23

DB12

LD1

LD0

DAC Select 1

DAC Select 0

PD0

D15

D14

D13

D12

DB11

DB0

D11

D10

Submit Documentation Feedback

Product Folder Link(s): DAC8564

DAC8564IAPWR 数据表(PDF) 27 Page - Texas Instruments

DAC8564IAPWR 数据表(HTML) 27 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

数据表下载