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PIN CONFIGURATIONS

V

A

OUT

LDAC

ENABLE

A1

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

DAC8564

V

B

OUT

V

H/V

OUT

REF

REF

AV

DD

V

L

REF

GND

V

C

OUT

V

D

OUT

A0

IOV

DD

D

IN

SCLK

SYNC

DAC8564

SBAS403A – JUNE 2007 – REVISED NOVEMBER 2007

PW PACKAGE

TSSOP-16

(Top View)

PIN DESCRIPTIONS

PIN

NAME

DESCRIPTION

1

Analog output voltage from DAC A

2

Analog output voltage from DAC B

3

Positive reference input / reference output 2.5V if internal reference used

4

Power supply input, 2.7V to 5.5V

5

Negative reference input

6

GND

Ground reference point for all circuitry on the part

7

Analog output voltage DAC C

8

Analog output voltage DAC D

Level-triggered control input (active low). This is the frame synchronization signal for the input data. When SYNC goes

low, it enables the input shift register, and data are sampled on subsequent falling clock edges. The DAC output

9

SYNC

updates following the 24th clock. If SYNC is taken high before the 24th clock edge, the rising edge of SYNC acts as

an interrupt, and the write sequence is ignored by the DAC8564. Schmitt-Trigger logic Input.

10

SCLK

Serial clock input. Data can be transferred at rates up to 50MHz. Schmitt-Trigger logic Input.

Serial data input. Data are clocked into the 24-bit input shift register on each falling edge of the serial clock input.

11

Schmitt-Trigger logic Input.

12

Digital input-output power supply

13

A0

Address 0—sets device address; see Table 5.

14

A1

Address 1—sets device address; see Table 5.

15

ENABLE

Active low, ENABLE low connects the SPI interface to the serial port

16

LDAC

Load DACs; rising edge triggered, loads all DAC registers

Copyright © 2007, Texas Instruments Incorporated

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Product Folder Link(s): DAC8564