DAC8564ICPW datasheet(37/46 Pages) TI

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MICROPROCESSOR INTERFACING

DAC8564 to an 8051 Interface

SYNC

DAC8564(1)

SCLK

NOTE:(1)Additionalpinsomittedforclarity.

Microwire

(1)

DAC8564 to 68HC11 Interface

PC7

SCK

MOSI

SYNC

DAC8564(1)

SCLK

NOTE:(1)Additionalpinsomittedforclarity.

68HC11

(1)

P3.3

TXD

RXD

SYNC

DAC8564(1)

SCLK

NOTE:(1)Additionalpinsomittedforclarity.

80C51/80L51

(1)

DAC8564 to Microwire Interface

DAC8564

SBAS403A – JUNE 2007 – REVISED NOVEMBER 2007

Figure 101 shows a serial interface between the

DAC8564 and a typical 8051-type microcontroller.

The setup for the interface is as follows: TXD of the

8051 drives SCLK of the DAC8564, while RXD drives

the serial data line of the device. The SYNC signal is

derived from a bit-programmable pin on the port of

Figure 102. DAC8564 to Microwire Interface

the 8051; in this case, port line P3.3 is used. When

data are to be transmitted to the DAC8564, P3.3 is

taken low. The 8051 transmits data in 8-bit bytes;

thus, only eight falling clock edges occur in the

Figure 103 shows a serial interface between the

transmit cycle. To load data to the DAC, P3.3 is left

DAC8564 and the 68HC11 microcontroller. SCK of

low after the first eight bits are transmitted; then, a

the 68HC11 drives the SCLK of the DAC8564, while

second write cycle is initiated to transmit the second

the MOSI output drives the serial data line of the

byte of data. P3.3 is taken high following the

DAC. The SYNC signal derives from a port line

completion of the third write cycle. The 8051 outputs

(PC7), similar to the 8051 diagram.

the serial data in a format that has the LSB first. The

DAC8564 requires its data with the MSB as the first

bit received. The 8051 transmit routine must therefore

take this requirement into account, and mirror the

data as needed.

Figure 103. DAC8564 to 68HC11 Interface

The 68HC11 should be configured so that its CPOL

bit is '0' and its CPHA bit is '1'. This configuration

causes data appearing on the MOSI output to be

Figure 101. DAC8564 to 80C51/80L51 Interface

valid on the falling edge of SCK. When data are

being transmitted to the DAC, the SYNC line is held

low

(PC7).

Serial

data

from

the

68HC11

are

transmitted in 8-bit bytes with only eight falling clock

Figure 102 shows an interface between the DAC8564

edges occurring in the transmit cycle. (Data are

and any Microwire-compatible device. Serial data are

transmitted MSB first.) In order to load data to the

shifted out on the falling edge of the serial clock and

DAC8564, PC7 is left low after the first eight bits are

are clocked into the DAC8564 on the rising edge of

transferred; then, a second and third serial write

the SK signal.

operation are performed to the DAC. PC7 is taken

high at the end of this procedure.

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