DAC8564ICPWR datasheet(30/46 Pages) TI

30 / 46 page

www.ti.com

ENABLE PIN

POWER-DOWN MODES

DAC Power-Down Commands

OUT

Amplifier

Resistor

String

DAC

Power-Down

Circuitry

Resistor

Network

DAC8564

SBAS403A – JUNE 2007 – REVISED NOVEMBER 2007

at 5.5V with an input code = 32768. The reference

current is included with the operation of all four

For normal operation, the enable pin must be driven

DACs. However, for the three power-down modes,

to a logic low. If the enable pin is driven high, the

the supply current falls to 1.3

µA at 5.5V (0.5µA at

DAC8564 stops listening to the serial port. However,

3.6V). Not only does the supply current fall, but the

SCLK, SYNC, and DIN must not be kept floating, but

output stage is also internally switched from the

must be at some logic level. This feature can be

output of the amplifier to a resistor network of known

useful for applications that share the same serial port.

values.

The advantage of this switching is that the output

impedance of the device is known while it is in

The DAC8564 has two separate sets of power-down

power-down mode. As described in Table 6, there are

commands. One set is for the DAC channels and the

three different power-down options. VOUT can be

other set is for the internal reference. For more

connected internally to GND through a 1k

Ω resistor, a

information on powering down the reference, see the

100k

Ω resistor, or open circuited (High-Z). The output

Enable/Disable Internal Reference section.

stage is shown in Figure 96. In other words, DB16,

DB15, and DB14 = '111' represent a power-down

condition with Hi-Z output impedance for a selected

channel. '101' represents a power-down condition

The DAC8564 uses four modes of operation. These

with 1k

Ω output impedance, and '110' represents a

modes are accessed by setting three bits (PD2, PD1,

power-down condition with 100k

Ω output impedance.

and PD0) in the shift register. Table 6 shows how to

control the operating mode with data bits PD0

(DB16), PD1 (DB15), and PD2 (DB14).

Table 6. DAC Operating Modes

PD0

PD1

PD2

(DB16)

(DB15)

(DB14)

DAC OPERATING MODES

Normal operation

Output typically 1k

Ω to GND

Output typically 100 k

Ω to GND

Output high-impedance

The DAC8564 treats the power-down condition as

Figure 96. Output Stage During Power-Down

data; all the operational modes are still valid for

power-down. It is possible to broadcast a power-down

All analog channel circuitries are shut down when the

condition to all the DAC8564s in a system; it is also

power-down

mode

exercised.

However,

the

possible to simultaneously power-down a channel

contents of the DAC register are unaffected when in

while updating data on other channels.

power down. The time required to exit power-down is

When the PD0 bit is set to '0', the device works

typically 2.5

µs for V

DD = 5V, and 5µs for VDD = 3V.

normally with its typical current consumption of 1mA

See the Typical Characteristics for more information.

Submit Documentation Feedback

Product Folder Link(s): DAC8564

DAC8564ICPWR 数据表(PDF) 30 Page - Texas Instruments

DAC8564ICPWR 数据表(HTML) 30 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

数据表下载