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TS3121AIYLT 数据表(PDF) 22 Page - STMicroelectronics

部件名 TS3121AIYLT
功能描述  Rail-to-rail, open-drain comparator with embedded fail-safe input/output
PDF  34 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

TS3121AIYLT 数据表(HTML) 22 Page - STMicroelectronics

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Guaranteed turn-on time
The TS3121 is tested in production for a guaranteed start-up time. Once the supply voltage crosses the minimum
value of VCC_min_operating = 1.7 V, the output voltage is settled in a stable condition within a maximum delay of
tturn-on = 15 µs. For low power applications, the supply voltage of the TS3121 can be disconnected when the
device is not in use. During shutdown (VCC = 0 V), because of its fail-safe structure, the input and output pins can
stay biased. In applications with switched Vcc, care should be taken to keep the Vcc ramp-up below 0.5 V/µs to
prevent false triggering of the integrated ESD protection circuit.
Figure 50. Turn-on timing diagram
VID
VCC
VOUT
1.5 V
turn-on time (tturn-on)
VOL
0V
-100mV
VCC_operating
VOH
0V
XXXX
50 %
Propagation delay
There is a delay between when the input crosses the reference voltage and the output responds. This is called
the propagation delay. Propagation delay can be different between high-to-low and low-to-high input transitions.
This is shown as tPLH and tPHL in Figure 51 and is measured from the mid-point of the input to the midpoint of the
output. Note that for open-drain comparators, the output rise time trise and tPLH strongly depend on the pull-up
circuit connected to the output pin.
Figure 51. Propagation delay
VIN :
Vref
Vref - 100mV
Vref + 100mV
VOUT :
VOL
VOH
tPLH
tPHL
trise
90%
10%
10%
90%
tfall
+
V+
V-
VIN
Vref
VOUT
50%
50%
TS3121, TS3121A
Application information
DS14484 - Rev 2
page 22/34



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