TMPR4938 datasheet(13/716 Pages) TOSHIBA

13 / 716 page

Table of Contents

18.3.4

NAND Flash Memory IPL Control Information...............................................................................18-11

18.3.5

Data configuration of NAND Flash Memory .................................................................................. 18-17

18.3.6

NAND Flash Memory IPL Error Handling ..................................................................................... 18-26

19. On-Chip SRAM .................................................................................................................................................... 19-1

19.1

Characteristics.............................................................................................................................................. 19-1

19.2

Block diagram.............................................................................................................................................. 19-1

19.3

Detailed explanation .................................................................................................................................... 19-2

19.3.1

Base address ...................................................................................................................................... 19-2

19.3.2

Access cycle count............................................................................................................................. 19-2

19.4

Register ........................................................................................................................................................ 19-3

19.4.1

On-chip SRAM Control Register (SRAMCR : 0x6000) ................................................................... 19-3

20. NAND Flash Memory Controller ......................................................................................................................... 20-1

20.1

Features ........................................................................................................................................................ 20-1

20.2

Block diagram.............................................................................................................................................. 20-1

20.3

Detailed operation ........................................................................................................................................ 20-2

20.3.1

Accessing NAND flash memory ....................................................................................................... 20-2

20.3.2

ECC control ....................................................................................................................................... 20-5

20.4

Registers....................................................................................................................................................... 20-6

20.4.1

NAND Flash Memory Data Transfer Register (NDFDTR) 0x5000 .................................................. 20-6

20.4.2

NAND Flash Memory Mode Control Register (NDFMCR) 0x5008................................................. 20-7

20.4.3

NAND Flash Memory Status Register (NDFSR) 0x5010 ................................................................. 20-8

20.4.4

NAND Flash Memory Interrupt Status Register (NDFISR) 0x5018 ................................................. 20-9

20.4.5

NAND Flash Memory Interrupt Mask Register (NDFIMR) 0x5020 .............................................. 20-10

20.4.6

NAND Flash Memory Strobe Pulse Width Register (NDFSPR) 0x5028 .........................................20-11

20.4.7

NAND Flash Memory Reset Register (NDFRSTR) 0x5030 ........................................................... 20-12

20.5

Timing diagram.......................................................................................................................................... 20-13

20.5.1

Command cycles and address cycles ............................................................................................... 20-13

20.5.2

Data read cycles ............................................................................................................................... 20-14

20.5.3

Data write cycles.............................................................................................................................. 20-15

20.6

NAND flash memory connection example ................................................................................................ 20-16

21. Extended EJTAG Interface ................................................................................................................................... 21-1

21.1

Extended EJTAG Interface .......................................................................................................................... 21-1

21.2

JTAG Boundary Scan Test .......................................................................................................................... 21-2

21.2.1

JTAG Controller and Register ........................................................................................................... 21-2

21.2.2

Instruction Register............................................................................................................................ 21-3

21.2.3

Boundary Scan Register..................................................................................................................... 21-3

21.2.4

Device ID Register ............................................................................................................................ 21-6

21.3

Initializing the Extended EJTAG Interface .................................................................................................. 21-7

22. Electrical Characteristics ...................................................................................................................................... 22-1

22.1

Absolute maximum rating (*1) .................................................................................................................... 22-1

22.2

Recommended operating conditions ............................................................................................................ 22-1

22.3

DC characteristics ........................................................................................................................................ 22-2

22.3.1

DC characteristics of pins other than PCI Interface pins ................................................................... 22-2

22.3.2

DC characteristics of PCI Interface pins............................................................................................ 22-3

22.4

PLL power.................................................................................................................................................... 22-4

22.4.1

PLL power connection example ........................................................................................................ 22-4

22.5

AC characteristics ........................................................................................................................................ 22-5

22.5.1

MASTERCLK AC characteristics ..................................................................................................... 22-5

22.5.2

Power on AC characteristics .............................................................................................................. 22-5

22.5.3

SDRAM Interface AC characteristics ................................................................................................ 22-6

22.5.4

External Bus Interface AC characteristics ......................................................................................... 22-8

22.5.5

PCI Interface AC characteristics (66 MHz) .......................................................................................22-9

22.5.6

PCI Interface AC characteristics (33 MHz) .......................................................................................22-9

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