TMP93CS44 datasheet(29/224 Pages) TOSHIBA

29 / 224 page

TMP93CS44/S45

2004-02-10

93CS44-27

3. IDLE1 mode

In the IDLE1 mode, only the internal oscillator operates. The system clock in

the MCU stops, the CLK pin is fixed at the level “H” in the output enable

(CKOCR<CLKEN>

= “1”).

In the halt state, and interrupt request is sampled asynchronously with the

system clock, however the halt release (Restart of operation) is performed

synchronously with it.

IDLE1 mode is released by external interrupts (NMI, INT0). (See Table 3.3.5

“Halt Releasing Source and Halt Releasing Operation”.)

When the IDLE1 mode is used, setting TRUN<PRRUN> to “0” to stop 9-bit

prescaler before “HALT” instruction reduces the power consumption.

Figure 3.3.7 illustrates the timing for releasing the halt state by interrupts in

the IDLE1 mode.

Figure 3.3.7 Timing Chart of Halt Released by Interrupts in IDLE1 Mode

Address

Data

Address

Data

IDLE1 mode

CLK

A0 to A23

ALE

AD0 to AD15

NMI

INT0

(Level)

INT0

(Rising edge)

Address

+ 2

Address

TMP93CS44 数据表(PDF) 29 Page - Toshiba Semiconductor

TMP93CS44 数据表(HTML) 29 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

TMP93CS44 数据表(PDF) 29 Page - Toshiba Semiconductor

TMP93CS44 数据表(HTML) 29 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载