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are trademarks of their respective owners.

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

Unlimited Designs

license allows using IP

Core in unlimited number of FPGA bitstreams

and ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time of use

limitations.

●

○

Single Design license for

VHDL, Verilog source code called HDL

Source

Encrypted, or plain text EDIF called Netlist

○

●

○

○

●

○

○

Unlimited Designs license for

HDL Source

Netlist

Upgrade from

Netlist to HDL Source

Single Design to Unlimited Designs

SYMBOL

datai(31:0)

datao(31:0)

en

rst

clk

ofo

ufo

ifo

PINS DESCRIPTI O N

PIN

TYPE

DESCRIPTION

clk

Input Global system clock

rst

Input Global system reset

en

Input Enable computing

datai[31:0]

Input Data bus input

datao[31:0]

Output Data bus output

ofo

Output Overflow flag

ufo

Output Underflow flag

ifo

Output Invalid result flag

BLOCK DIAGRAM

datai(31:0)

datao(31:0)

en

rst

clk

ofo

ufo

ifo

Argument

Checker

Main FP

Pipelined Unit

Result

Composer

Arguments Checker

- performs input data

analyze against IEEE-754 number standard

compliance. The appropriate numbers and

information about the input data classes are

given as the results to Main FP Pipelined

Unit.

Main FP Pipelined Unit

- performs floating

point to integer conversion. Gives the com-

plex information about the results to Result

Composer module.

Result Composer

- performs result rounding

function, data alignment to IEEE-754 stan-

dard, and the final flags setting.