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SYMBOL

PINS DESCRIPTI O N

PIN

TYPE

DESCRIPTION

clk

Input

Global system clock

rst

Input

Global system reset

cs

Input

Chip select for read/write

datai[31:0]

1

Input

Data bus input

addr[4:2]

2

Input

Register address to read/write

we

Input

Data write enable

datao[31:0]

1

Output Data bus output

int

Output Interrupt request indicator

1 – data bus can be configured as 8-, 16- or 32- bit

depends on processor’s bus size

2 – address bus is aligned to work with 8- (3:0), 16-

(3:1) or 32- (4:2) bit processors

BLOCK DIAGRAM

Mantissa –

performs operations on mantissa

part of number. The addition, subtraction,

multiplication, division, square root, compari-

son and conversion operations are executed

in this module. It contains mantissas and

work registers.

Exponent –

performs operations on expo-

nent part of number. The addition, subtrac-

tion, shifting, comparison and conversion

operations are executed in this module. It

contains exponents and work registers.

Align –

performs the numbers analyze

against IEEE-754 standard compliance. In-

formation about the data classes are passed

as result to appropriate internal module.

Shifter –

performs mantissa shifting during

normalization, denormalization operations.

Information about shifted-out bits are stored

for rounding process.

Control Unit –

manages execution of all

instructions and internal operation required to

execute particular function.

Interface –

makes interface between exter-

nal device and DFPAU internal 32-bit mod-

ules. It contains data, control and status reg-

isters. It can be configured to work with 8-,

16- and 32-bit processors.

PERFORMANCE

The following table gives a survey about

the Core area and performance in the AL-

TERA® devices after Place & Route (all key

features have been included):

Device

Speed

grade

Logic Cells

APEX20KE

-1

2640

48 MHz

APEX20KC

-7

2640

57 MHz

APEX-II

-7

2640

70 MHz

CYCLONE

-6

2410

91 MHz

CYCLONE-II

-6

2280

96 MHz

STRATIX

-5

2210

115 MHz

STRATIX-II

-3

1680

169 MHz

Core performance in ALTERA® devices

Mantissa

Align

Shifter

Exponent

Control

Unit

clk

rst

irq

we

cs

Interface

irq

we

rst

clk

cs