数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

DFPAU-DP 数据表(PDF) 2 Page - Digital Core Design

部件名 DFPAU-DP
功能描述  Floating Point Arithmetic Coprocessor Double Precision
PDF  6 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  DCD [Digital Core Design]
网页  http://www.digitalcoredesign.com
标志 DCD - Digital Core Design

DFPAU-DP 数据表(HTML) 2 Page - Digital Core Design

  DFPAU-DP Datasheet HTML 1Page - Digital Core Design DFPAU-DP Datasheet HTML 2Page - Digital Core Design DFPAU-DP Datasheet HTML 3Page - Digital Core Design DFPAU-DP Datasheet HTML 4Page - Digital Core Design DFPAU-DP Datasheet HTML 5Page - Digital Core Design DFPAU-DP Datasheet HTML 6Page - Digital Core Design  
Zoom Inzoom in Zoom Outzoom out
 2 / 6 page
background image
All trademarks mentioned in this document
are trademarks of their respective owners.
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
FCLD, FILD
– 8-bit, 16-bit integer to dou-
ble
KEY FEATURES
Direct replacement
for C double, float
software functions such as: +, -, *, /,==,
!=,>=, <=, <, >
Configurability of all available functions
C interface supplied for all popular compil-
ers: GNU C/C++, 8051 compilers
No programming required
IEEE-754 Double precision real format
support – double type
IEEE-754 Single precision real format
support – float type
8-bit, 16-bit 32-bit and 52-bit integers for-
mat supported – integer types
Flexible arguments and result registers
location
Performs the following functions:
FADD, FSUB
– addition, subtraction
FMUL, FDIV
– multiplication, division
FSQRT
– square root
FXAM
– examine input data
FUCOM
– comparison
FLLD, FELD
– 32-bit, 52-bit integer to
double
FCST, FIST
– double to 8-bit, 16-bi inte-
ger
FLST, FEST
– double to 32-bit, 52-bit in-
teger
FFLD
– float to double
FFST
– double to float
Exceptions built-in routines
Masks each exception indicator:
Precision lack PE
Underflow result UE
Overflow result OE
Invalid operand IE
Division by zero ZE
Denormal operand DE
Fully configurable
Fully synthesizable, static synchronous
design with no internal tri-states
DELIVERABLES
Source code:
VHDL Source Code or/and
VERILOG Source Code or/and
Encrypted Netlist or/and
plain text EDIF netlist
VHDL & VERILOG test bench environ-
ment
Active-HDL automatic simulation mac-
ros
NCSim automatic simulation macros
ModelSim automatic simulation macros
Tests with reference responses
Technical documentation
Installation notes
HDL core specification
Datasheet
Synthesis scripts
Example application
Technical support
IP Core implementation support
3 months maintenance
Delivery the IP Core updates, minor
and major versions changes
Delivery the documentation updates
Phone & email support



Html Pages

1 2 3 4 5 6


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com