All trademarks mentioned in this document

are trademarks of their respective owners.

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

tation. It also permits FPGA prototyping be-

fore ASIC production.

Unlimited Designs

license allows using IP

Core in unlimited number of FPGA bitstreams

and ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time of use

limitations.

●

○

Single Design license for

VHDL, Verilog source code called HDL

Source

Encrypted, or plain text EDIF called Netlist

○

●

○

○

●

○

○

Unlimited Designs license for

HDL Source

Netlist

Upgrade from

Netlist to HDL Source

Single Design to Unlimited Designs

SYMBOL

datai(31:0)

datao(31:0)

en

rst

clk

PINS DESCRIPTI O N

PIN

TYPE

DESCRIPTION

clk

Input Global system clock

rst

Input Global system reset

en

Input Enable computing

datai[31:0]

Input Data bus input

datao[31:0]

Output Data bus output

BLOCK DIAGRAM

datai(31:0)

datao(31:0)

en

rst

clk

Argument

Checker

Main FP

Pipelined Unit

Result

Composer

Arguments Checker

- performs input data

analyze against IEEE-754 number standard

compliance. The appropriate numbers and

information about the input data classes are

given as the results to Main FP Pipelined

Unit.

Main FP Pipelined Unit

- performs integer to

floating point conversion. Gives the complex

information about the results to Result Com-

poser module.

Result Composer

- performs result rounding

function, and data alignment to IEEE-754

standard.

PERFORMANCE

The following table gives a survey about the

Core area and performance in the ALTERA®

devices after Place & Route :

Device

Speed

grade

Logic Cells

FLEX10KE

-1

570

83 MHz

ACEX1K

-1

570

80 MHz

APEX20K

-1

470

61 MHz

APEX20KE

-1

470

73 MHz

APEX20KC

-7

470

87 MHz

APEX-II

-7

470

103 MHz

MERCURY

-5

570

157 MHz

STRATIX

-5

400

150 MHz

CYCLONE

-6

385

156 MHz

STRATIX-II

-3

330

234 MHz

CYCLONE-II

-6

410

149 MHz

Core performance in ALTERA® devices