AM69 datasheet(8/326 Pages) TI1

8 / 326 page

If QSGMII is used on any SGMII Port 5 thru 8, then SGMII5/6/7/8 cannot be used for Ethernet functionality since all 4 internal CPSW

ports map to the selected QSGMII SERDES port.

AM69A94 (27mm)/AM6954 (27mm) CPSW supports up to 4 ports. The BGA and Pin Muxing limitations are shown in Pin Attributes

Table "A94 54" column.

(8)

Two simultaneous flash interfaces configured as OSPI0 and OSPI1, or HyperBus and OSPI1.

(9)

J784S4 is the base part number for the superset device. Software should constrain the features used to match the intended production

device.

(10) OSPI1 module only pins out 4 pins and is referred to as QSPI in some contexts.

(11) MCU_R5FSS0 includes Dual-Core R5F that provides Device Management functionality, and is reserved for executing TI provided

code.

R5FSS1 is a Dual-Core R5F that provides Multimedia Control functionality, and is reserved for executing TI provided code.

(12) The Deep Learning Accelerator C7x + MMA are reserved for executing TI provided code, and are not available for custom code.

(13) AM69A94 (27mm)/AM6954 (27mm) PCIe supports 1x4L or 2x2L options. The BGA and Pin Muxing limitations are shown in Pin

Attributes Table "A94 54" column.

(14) The A72SS Quad Core variant provides a single quad core cluster, namely A72SS0_CORE[3:0].

AM69A, AM69

SPRSP92D – FEBRUARY 2023 – REVISED DECEMBER 2024

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AM69 数据表(PDF) 8 Page - Texas Instruments