3 Pin Configuration and Functions

1

2

3

7

4

5

6

14

13

12

8

11

10

9

1A

1Y

2A

2Y

3A

3Y

GND

6A

6Y

5A

5Y

4A

V

CC

4Y

Figure 3-1. CD54ACT05 J Package, 14-Pin CDIP;

CD74ACT05 D, N, or PW Package; 14-Pin SOIC,

PDIP, or TSSOP (Top View)

1Y

2A

2Y

3A

3Y

GND

6A

6Y

5A

5Y

4A

4Y

PAD

1A

V

CC

2

3

4

5

6

7

13

12

11

10

9

8

1

14

Figure 3-2. CD74ACT05 BQA Package, 14-Pin

WQFN

Table 3-1. Pin Functions

PIN

I/O(1)

DESCRIPTION

NAME

CD74ACT05

CD54ACT05

BQA, D, N, PW

J

1A

1

1

I

1A Input

1Y

2

2

O

1Y Output

2A

3

3

I

2A Input

2Y

4

4

O

2Y Output

3A

5

5

I

3A Input

3Y

6

6

O

3Y Output

GND

7

7

—

Ground Pin

4Y

8

8

O

4Y Output

4A

9

9

I

4A Input

5Y

10

10

I

5Y Output

5A

11

11

I

5A Input

6Y

12

12

O

6Y Output

6A

13

13

I

6A Input

VCC

14

14

—

Power Pin

NC

—

—

—

No Connection

Thermal pad

—

Connect the GND pin to the exposed thermal pad for correct

operation. Connect the thermal pad to any internal PCB ground

plane using multiple vias for good thermal performance.

(1)

I = input, O = output, P = power, FB = feedback, GND = ground, N/A = not applicable

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CD54ACT05, CD74ACT05

SCHS311E – JANUARY 2001 – REVISED NOVEMBER 2024

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