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11 Layout

11.1 Layout Guidelines

REF50xxI, REF50xxAI

• Place the power-supply bypass capacitor as closely as possible to the supply and ground pins. The

recommended value of this bypass capacitor is from 1μF to 10μF. If necessary, additional decoupling

capacitance can be added to compensate for noisy or high-impedance power supplies.

• Place a 1μF noise filtering capacitor between the NR pin and ground.

• The output must be decoupled with a 1μF to 50μF capacitor. A resistor in series with the output capacitor is

optional. For better noise performance, the recommended ESR on the output capacitor is from 1Ω to 1.5Ω.

• A high-frequency, 1μF capacitor can be added in parallel between the output and ground to filter noise and

help with switching loads as data converters.

REF50xxEI

• Place the power-supply bypass capacitor as close as possible to the supply and ground pins. The

recommended value of this bypass capacitor is from 0.1μF to 10μF. If necessary, additional decoupling

capacitance can be added to compensate for noisy or high-impedance power supplies. The smallest

capacitor must be placed closest to the device

• Place a 0.1μF to 1μF class 1 noise filtering capacitor between the NR pin and ground

• The output must be decoupled with a 1μF to 100μF low ESR (maximum 1 Ω) capacitor.

11.2 Layout Example

DNC

TEMP

GND

DNC

OUT

TRIM/NR

Figure 11-1. Layout Example for REF50xxI,

REF50xxAI

Figure 11-2. Layout Example for REF50xxEI

11.3 Power Dissipation

The REF50xx family is specified to deliver current loads of ±10mA over the specified input voltage range. The

temperature of the device increases according to Equation 6:

TJ = TA + PD × θJA

(6)

where

• TJ = junction temperature (°C)

• TA = ambient temperature (°C)

• PD = power dissipated (W)

• θJA = junction-to-ambient thermal resistance (°C/W)

The REF50xx junction temperature must not exceed the absolute maximum rating of 150°C.

REF50, REF50E

SBOS410N – JUNE 2007 – REVISED MARCH 2025

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