TMP88CS34FG datasheet(77/215 Pages) TOSHIBA

77 / 215 page

TMP88CS34/CP34

2007-09-12

88CS34-77

Figure 2.7.3 Timer Mode Timing Chart

(2) Event counter mode

In this mode, the TC3 pin input pulses are used for counting up Either the rising on

falling edge can be selected with TC3ES (bit 0 in PMPXCR). The contents of TC3DRA are

compared with the contents of the up-counter. If a match is found, an INTTC3 interrupt is

generated and the counter is cleared. Match detect is executed on the falling edge of the

TC3 pin. A match can not be detected, and INTTC3 is not generated when the pulse is still

in a falling state.

The maximum applied frequency is shown in Table 2.7.2. Two or more machine cycles are

required for both the high and low levels of the pulse width.

The current contents of up-counter are loaded into TC3DRB by setting ACAP (bit 6 in

TC3CR) to “1” (Auto-capture funcion).

The contents of up-counter can be easily confirmed by executing the read instruction (RD

instruction) of TC3DRB. Loading the contents of up-counter is not synchronized with

counting up. The contents of over flow (FFH) and 00H can not be loaded correctly. It is

necessary to consider the count cycle.

Example: Generates an interrupt every 0.5 s, inputting 50 Hz pulses to the TC3 pin.

(TC3CR), 00001110B

;

Sets TC3 mode and source clock

(TC3DRA), 19H

;

0.5 s

÷ 1/50 = 25 = 19H

(TC3CR), 00011100B

;

Starts TC3

Table 2.7.2 Source Clock (External Clock) for Timer/Counter

Minimum applied frequency [Hz]

NORMAL, IDLE Mode

"H" width

2/fc

"L" width

2/fc

− 2

Up-counter

Timer register B

ACAP1

Capture

+ 1m + 2

(b) Auto-capture

Timer register B

INTTC3 interrupt

− 1n

+ 1

Capture

Count start

Source clock

Up-counter

Source clock

− 1 n 0

Match detect

Counter clear

(a) Timer Mode

− 1

+ 1m + 2

− 1

+ 1

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