STA538 datasheet(42/59 Pages) STMICROELECTRONICS

部件名	STA538

功能描述	2 x 1.3 W class-D amplifier with analog or digital input 2.0 multichannel digital audio processor with FFX

PDF	59 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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42 / 59 page

Registers

STA538

42/59

S2PCFG0

Serial-to-parallel audio interface configuration

Address:

0x0A

Type:

R/W

Buffer:

Reset:

0xD2

Description:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BICLK_STRB

LRCLK_LEFT

SHARE_BILR

MSB_FIRST

DATA_FORMAT[2:0]

MASTER_

MODE

7 BICLK_STRB:

0: bit clock strobe edge is falling edge, bit clock active edge is rising edge

1: bit clock strobe edge is rising edge, bit clock active edge is falling edge (default)

6 LRCLK_LEFT:

0: left/right clock is low for left channel, high for right channel

1: left/right clock is high for left channel, low for right channel (default)

5 SHARE_BILR:

0: default

1: left/right clock and bit clock are shared between serial-parallel interface and parallel-to-

serial interface, BICLKI and LRCLKI are used

4 MSB_FIRST:

0: LSB first

1: MSB first (default)

3:1 DATA_FORMAT[2:0]: serial interface protocol format:

000: left Justified

001: I2S (default)

010: right justified

100: PCM no delay

101: PCM delay

111: DSP

001: default

0 MASTER_MODE:

0: default

1: serial interface is in master mode

STA538 数据表(PDF) 42 Page - STMicroelectronics

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