Data Sheet

AD8488

Rev. A | Page 13 of 20

THEORY OF OPERATION

OVERVIEW

The AD8488 is a 128-channel AFE intended for interfacing thin film

transistor (TFT) detector panel arrays in various digital X-ray

applications (see Figure 1). The device includes a 128 dual stage,

charge conversion amplifiers, internal timing, and control circuitry,

a 128:1 differential output multiplexer, and an analog output buffer.

Only the detector panel and a minimal amount of analog circuitry are

required to complete a 128-channel analog X-ray interface. The

AD8488 AFE is packaged in a compact, 17 mm × 17 mm,

255-lead BGA.

Analog Amplifier

The AD8488 analog inputs are suitable for ac or dc connection to

128 X-ray detector panel outputs. The analog amplifier consists of

two stages: an integrator followed by a correlated double sampling

gain amplifier. Figure 16 is a simplified block diagram showing the

basic elements of an analog channel.

The characteristic CMOS high gate impedance of the integrator

minimizes source loading. Prior to sampling a gate line, all 128 mux

analog channels are initialized with RST, as shown in Figure 17.

During the 6.1 µs GRST period, the gain amplifier acquires the

reference level (2.048 V) and any low frequency ambient noise.

Just prior to gate sampling, both op amps are unlocked and the

feedback capacitors, CF1 and CF2, are connected. When a TFT gate

line is activated (reference the bottom signal, TFT_GATE, in

Figure 17), the charge of each detector cell is applied simultaneously

to all 128 MOSFET integrator circuits, which begin to ramp over a

12 µs interval. As seen in Figure 16, the op amps are biased at the

reference voltage, plus offset and low frequency noise error voltages.

Together, the resultant differential output voltage comprises the

CDS or correlated double sampled composite. Following the sampling

period, the pixel charges are stored, and the charge is held for the

next 133 clock cycles while the 128 channels are muxed and sampled

sequentially. As the channels are selected in sequence, their outputs

are applied to a dual channel, high precision, current feedback, high

frequency op amp. The AD8488 was designed to drive an ADC such

as the AD9244 differential input high speed converter.

The mux channels are enabled and selected by the timing inputs,

CK_ENa and CK_ENb. These two signals gate the clock and internal

counter that actually selects the mux channel. The multiplexers must

be read sequentially as one interprets from the CK_ENa and CK_ENb

lines in Figure 17. The read time for each channel is 1 clock cycle. The

timing signals, GATED CLKa and GATED CLKb, are developed

internally and are shown in Figure 17 for reference only.

Troubleshooting Channels

Using the TST_MODE enable pin, individual channels are accessible

for troubleshooting. Referring to Table 8, the channel address follows

two initialization words, 0x01 and 0x02, while the enable pin,

TST_MODE, is asserted high.

IN0 TO IN127

SWIRST

SWHOLD

TO

MUX

VREF

INTEGRATOR

GAIN

AMPLIFIER

CM

SWHOLD

SWGRST

SWGRST

CFx: FEEDBACK CAPACITOR

CH: HOLD CAPACITOR

GNSEL0

TO

GNSEL3

GNSEL0

TO

GNSEL3

R1 (×4)

R1 (×4)

CF1 (×4)

CF2 = 0.5pF

CF2 = 0.5pF

CH (×4)

CH (×4)

Figure 16. Block Diagram of an Integrator Channel