ADIN1101CCPZ-R7 datasheet(16/79 Pages) AD

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Data Sheet

ADIN1101

THEORY OF OPERATION

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Rev. A | 16 of 79

Autonegotiation Fail

On a 10BASE-T1L link, the autonegotiation can fail and can be

caused by various scenarios.

►

Configuration fault such as invalid leader/follower configuration

►

Link quality issues

►

Timeout in pages transmission

If the autonegotiation fails, the link remains down until the autone-

gotiation process is restarted and completed.

MANAGEMENT INTERFACE

The MII management interface provides a 2-wire serial interface

between a host controller or external MAC chip and the ADIN1101

allowing access to control and status information in the subsystem

and PHY core management registers.

The MII management interface consists of the following:

►

MDC: clock line

►

MDIO: bidirectional data line

►

PHYAD_0, PHYAD_1, PHYAD_2: PHY address selection

►

INT: configurable management interrupt

The interface is compatible with both IEEE Standard 802.3 Clause

22 and Clause 45 management frame structures (see the MDIO

Interface section).

MDI Circuitry

The MDI connects the ADIN1101 to the Ethernet network via a

twisted wire pair.

The ADIN1101 provides a two-pin MDI with internal termination

resistors and an internal hybrid to connect the ADIN1101 directly to

the Ethernet network via a twisted wire pair.

Figure 13, Figure 14, and Figure 15 show the topologies and values

for the components.

The component values are as follows:

►

D1, D2: protection components low capacitance (<5 pF), low-

voltage (standoff voltage ≥3.3 V) TVS.

►

C1, C2: 0.22 µF, 60 V rating. If a transformer with low inductance

is 350 µH, then C1 and C2 may need to increase to 0.47 µF (to

comply with droop specification per IEEE 802.3).

►

R7, R8: optional resistors preventing built up charge on the C1

and C2 capacitors (100 kΩ to ~ 1 MΩ).

►

C3, C4: 47 pF to 100 pF, ±5% tolerance.

►

D3: protection component low capacitance TVS (≤100 pF). It is

important that the TVS diode has low capacitance.

►

L1 transformer: provides galvanic isolation.

►

Must be able to operate in the frequency range from 100 kHz

to 20 MHz.

►

Inductance > 350 µH.

►

L2 common-mode inductor: ≥220 µH, low-leakage inductance

<0.5 µH.

►

L3 power inductor: power coupling for advanced physical layer

(APL) and non APL devices.

►

APL: >880 µH differentially to achieve 10% max droop.

►

Recommended >220 µH coupled inductor (two inductors on

a common magnetic core).

►

Or two >440 µH individual inductors.

►

Non APL: >160 µH differentially to achieve approximately 25%

max droop.

►

Recommended >47 µH coupled inductor (two inductors on

a common magnetic core).

►

Or two >100 µH individual inductors.

Note that an isolation transformer is present on the MDI transmis-

sion line, the parallel combination between the inductance of the

transformer and the total differential inductance of the power induc-

tor must be greater than 160 µH.

Figure 13. Typical MDI Circuitry with Capacitive Coupling for the ADIN1101

Figure 14. Typical MDI Circuitry with Galvanic Isolation for the ADIN1101

Figure 15. Typical MDI Circuitry with Power Coupling for the ADIN1101

Hardware Interrupt (INT)

The ADIN1101 can generate a hardware interrupt to a host control-

ler or external MAC chip using the INT pin.

PHY Status Interrupts

The following conditions can be selected to generate an interrupt:

►

MAC interface frame checker/generator interrupt

►

MAC interface buffers overflow/underflow interrupt

►

Autonegotiation status change interrupt

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