ST72F521 datasheet(106/215 Pages) STMICROELECTRONICS

106 / 215 page

ST72F521, ST72521B

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

Framing Error

A framing error is detected when:

– The stop bit is not recognized on reception at the

expected time, following either a de-synchroni-

zation or excessive noise.

– A break is received.

When the framing error is detected:

– the FE bit is set by hardware

– Data is transferred from the Shift register to the

SCIDR register.

– No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself

generates an interrupt.

The FE bit is reset by a SCISR register read oper-

ation followed by a SCIDR register read operation.

10.6.4.4 Conventional Baud Rate Generation

The baud rate for the receiver and transmitter (Rx

and Tx) are set independently and calculated as

follows:

with:

PR = 1, 3, 4 or 13 (see SCP[1:0] bits)

TR = 1, 2, 4, 8, 16, 32, 64,128

(see SCT[2:0] bits)

RR = 1, 2, 4, 8, 16, 32, 64,128

(see SCR[2:0] bits)

All these bits are in the SCIBRR register.

Example: If fCPU is 8 MHz (normal mode) and if

PR=13 and TR=RR=1, the transmit and receive

baud rates are 38400 baud.

Note: the baud rate registers MUST NOT be

changed while the transmitter or the receiver is en-

abled.

10.6.4.5 Extended Baud Rate Generation

The extended prescaler option gives a very fine

tuning on the baud rate, using a 255 value prescal-

er, whereas the conventional Baud Rate Genera-

tor retains industry standard software compatibili-

ty.

The extended baud rate generator block diagram

is described in the Figure 62.

The output clock rate sent to the transmitter or to

the receiver will be the output from the 16 divider

divided by a factor ranging from 1 to 255 set in the

SCIERPR or the SCIETPR register.

Note: the extended prescaler is activated by set-

ting the SCIETPR or SCIERPR register to a value

other than zero. The baud rates are calculated as

follows:

with:

ETPR = 1,..,255 (see SCIETPR register)

ERPR = 1,.. 255 (see SCIERPR register)

10.6.4.6 Receiver Muting and Wake-up Feature

In multiprocessor configurations it is often desira-

ble that only the intended message recipient

should actively receive the full message contents,

thus reducing redundant SCI service overhead for

all non addressed receivers.

The non addressed devices may be placed in

sleep mode by means of the muting function.

Setting the RWU bit by software puts the SCI in

sleep mode:

All the reception status bits can not be set.

All the receive interrupts are inhibited.

A muted receiver may be awakened by one of the

following two ways:

– by Idle Line detection if the WAKE bit is reset,

– by Address Mark detection if the WAKE bit is set.

Receiver wakes-up by Idle Line detection when

the Receive line has recognised an Idle Frame.

Then the RWU bit is reset by hardware but the

IDLE bit is not set.

Receiver wakes-up by Address Mark detection

when it received a “1” as the most significant bit of

a word, thus indicating that the message is an ad-

dress. The reception of this particular word wakes

up the receiver, resets the RWU bit and sets the

RDRF bit, which allows the receiver to receive this

word normally and to use it as an address word.

Caution: In Mute mode, do not write to the

SCICR2 register. If the SCI is in Mute mode during

the read operation (RWU=1) and a address mark

wake up event occurs (RWU is reset) before the

write operation, the RWU bit will be set again by

this write operation. Consequently the address

byte is lost and the SCI is not woken up from Mute

mode.

Tx =

(16*PR)*TR

fCPU

Rx =

(16*PR)*RR

fCPU

Tx =

16*ETPR*(PR*TR)

fCPU

Rx =

16*ERPR*(PR*RR)

fCPU

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