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ST72F521 数据表(PDF) 168 Page - STMicroelectronics

部件名 ST72F521
功能描述  80/64-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE
PDF  215 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST72F521 数据表(HTML) 168 Page - STMicroelectronics

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OPERATING CONDITIONS (Cont’d)
12.3.2 Operating Conditions with Low Voltage Detector (LVD)
Subject to general operating conditions for VDD, fCPU, and TA.
Notes:
1. Data based on characterization results, tested in production for ROM devices only.
2. When VtPOR is faster than 100 µs/V, the Reset signal is released after a delay of max. 42µs after VDD crosses the
VIT+(LVD) threshold.
3. If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range.
Below 3.8V, device operation is not guaranteed.
12.3.3 Auxiliary Voltage Detector (AVD) Thresholds
Subject to general operating conditions for VDD, fCPU, and TA.
1. Data based on characterization results, tested in production for ROM devices only.
12.3.4 External Voltage Detector (EVD) Thresholds
Subject to general operating conditions for VDD, fCPU, and TA.
1. Data based on characterization results, not tested in production.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIT+(LVD)
Reset release threshold
(VDD rise)
VD level = High in option byte
4.0 1)
4.2
4.5
V
VD level = Med. in option byte3)
VD level = Low in option byte3)
3.55 1)
2.95 1)
3.75
3.15
4.01)
3.351)
VIT-(LVD)
Reset generation threshold
(VDD fall)
VD level = High in option byte
3.8
4.0
4.25 1)
VD level = Med. in option byte3)
VD level = Low in option byte3)
3.351)
2.81)
3.55
3.0
3.751)
3.15 1)
Vhys(LVD)
LVD voltage threshold hysteresis
1)
VIT+(LVD)-VIT-(LVD)
150
200
250
mV
VtPOR
VDD rise time
1)2)
Flash device, LVD enabled
6
µs/V
20ms/V
ROM device, LVD enabled
6
µs/V
100ms/V
tg(VDD)
VDD glitches filtered (not detect-
ed) by LVD 1)
40
ns
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIT+(AVD)
1
⇒0 AVDF flag toggle threshold
(VDD rise)
VD level = High in option byte
4.4 1)
4.6
4.9
V
VD level = Med. in option byte
VD level = Low in option byte
3.95 1)
3.4 1)
4.15
3.6
4.41)
3.81)
VIT-(AVD)
0
⇒1 AVDF flag toggle threshold
(VDD fall)
VD level = High in option byte
4.2
4.4
4.65 1)
VD level = Med. in option byte
VD level = Low in option byte
3.751)
3.21)
4.0
3.4
4.2 1)
3.6 1)
Vhys(AVD)
AVD voltage threshold hysteresis
VIT+(AVD)-VIT-(AVD)
200
mV
∆VIT-
Voltage drop between AVD flag set
and LVD reset activated
VIT-(AVD)-VIT-(LVD)
450
mV
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIT+(EVD)
1
⇒0 AVDF flag toggle threshold
(VDD rise)
1)
1.15
1.26
1.35
V
VIT-(EVD)
0
⇒1 AVDF flag toggle threshold
(VDD fall)
1)
1.1
1.2
1.3
Vhys(EVD)
EVD voltage threshold hysteresis
VIT+(EVD)-VIT-(EVD)
200
mV



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