ST72F521 datasheet(177/215 Pages) STMICROELECTRONICS

部件名	ST72F521

功能描述	80/64-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE

PDF	215 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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ST72F521, ST72521B

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CLOCK CHARACTERISTICS (Cont’d)

12.5.5 PLL Characteristics

Note:

1. Data characterized but not tested.

The user must take the PLL jitter into account in the application (for example in serial communication or

sampling of high frequency signals). The PLL jitter is a periodic effect, which is integrated over several

CPU cycles. Therefore the longer the period of the application signal, the less it will be impacted by the

PLL jitter.

Figure 94 shows the PLL jitter integrated on application signals in the range 125kHz to 4MHz. At frequen-

cies of less than 125KHz, the jitter is negligible.

Figure 94. Integrated PLL Jitter vs signal frequency1

Note 1: Measurement conditions: fCPU = 8MHz.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fOSC

PLL input frequency range

MHz

∆ fCPU/ fCPU Instantaneous PLL jitter 1)

ROM device,

fOSC = 4 MHz.

0.7

Flash device,

fOSC = 4 MHz.

1.0

2.5

Flash device,

fOSC = 2 MHz.

2.5

4.0

0.2

0.4

0.6

0.8

1.2

4 MHz

2 MHz

1 MHz 500 kHz 250 kHz 125 kHz

Application Frequency

+/-Jitter (%)

FLASH typ

ROM max

ROM typ

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