ST72F521 datasheet(212/215 Pages) STMICROELECTRONICS

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ST72F521, ST72521B

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KNOWN LIMITATIONS (Cont’d)

15.1.6 SCI Wrong Break duration

Description

A single break character is sent by setting and re-

setting the SBK bit in the SCICR2 register. In

some cases, the break character may have a long-

er duration than expected:

- 20 bits instead of 10 bits if M=0

- 22 bits instead of 11 bits if M=1.

In the same way, as long as the SBK bit is set,

break characters are sent to the TDO pin. This

may lead to generate one break more than expect-

ed.

Occurrence

The occurrence of the problem is random and pro-

portional to the baudrate. With a transmit frequen-

19200

baud

(fCPU=8MHz and SCI-

BRR=0xC9), the wrong break duration occurrence

is around 1%.

Workaround

If this wrong duration is not compliant with the

communication protocol in the application, soft-

ware can request that an Idle line be generated

before the break character. In this case, the break

duration is always correct assuming the applica-

tion is not doing anything between the idle and the

break. This can be ensured by temporarily disa-

bling interrupts.

The exact sequence is:

- Disable interrupts

- Reset and Set TE (IDLE request)

- Set and Reset SBK (Break Request)

- Re-enable interrupts

15.1.7 16-bit Timer PWM Mode

In PWM mode, the first PWM pulse is missed after

writing the value FFFCh in the OC1R register

(OC1HR, OC1LR). It leads to either full or no PWM

during a period, depending on the OLVL1 and

OLVL2 settings.

15.1.8 CAN Cell Limitations

x=limitation present

1For details see section 10.8.5 on page 146

2Software workaround possible using modified

WKPS bit.

3Functionality modified for Unexpected Message

Transmission workaround in Flash.

4Limitation present on ROM Rev W and Rev Z.

Not present in Flash and ROM Rev Y.

15.1.9 I2C Multimaster

In multimaster configurations, if the ST7 I2C re-

ceives a START condition from another I2C mas-

ter after the START bit is set in the I2CCR register

and before the START condition is generated by

the ST7 I2C, it may ignore the START condition

from the other I2C master. In this case, the ST7

master will receive a NACK from the other device.

On reception of the NACK, ST7 can send a re-start

and Slave address to re-initiate communication

Limitation

Flash

ROM

Omitted SOF bit

CPU write access

(more than one cycle)

corrupts CAN frame

Unexpected Mes-

sage transmission

Bus Off State Not En-

tered

WKPS Functionality

ST72F521 数据表(PDF) 212 Page - STMicroelectronics

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