13892 datasheet(68/158 Pages) FREESCALE

68 / 158 page

FUNCTIONAL DEVICE OPERATION

OPERATING MODES

Analog Integrated Circuit Device Data



Freescale Semiconductor

MC13892

Figure 13. Power Gating Diagram

MEMORY HOLD POWER GATING

As with the User Off power gating strategy described previously, Memory Hold power gating is intended to allow isolation of

the SW4 power domain, to selected circuitry in Low-power modes while cutting off the switcher domain from other peripheral

loads. The only difference is that processor supplies SW1, and/or SW2, and/or SW3, are shut down in Memory Hold, so just the

external memory is maintained in self refresh mode.

An external NMOS is to be placed between the direct-connected memory supply and any peripheral loading. The PWGTDRV2

pin controls the gate of the external NMOS and is normally pulled up to a charge pumped voltage (~5.0 V). During Memory Hold

or User Off, PWGTDRV2 will go low to turn off the NMOS switch and isolate memory on the SW4 power domain.

Figure 14. Memory Hold Circuit

EXITING FROM LOW-POWER OFF MODES

When a Turn On event occurs, any switchers that are active through Low-power Off modes will stay in PFM mode at their

Standby voltage set points until the applicable time slot of the startup sequencer. At that point, the respective switcher is updated

for the PUMSx defined default state for mode and voltage. Subsequent closing of the power gate switches will be coordinated

by software to complete restoration of the full system power tree.

13892 数据表(PDF) 68 Page - Freescale Semiconductor, Inc