| 数据搜索系统,热门电子元器件搜索 |
|
ACT4921 数据表(PDF) 13 Page - Qorvo, Inc |
|
|
|||||||||||||||||||||||||||||
ACT4921 数据表(HTML) 13 Page - Qorvo, Inc |
|
13 / 35 page ![]() Data Sheet Rev. B, January 2020 | Subject to change without notice 13 of 35 www.qorvo.com © 2020 Qorvo US, Inc. All rights reserved. ACT4921 Power Loss Protection with 6A eFuse I2C INTERFACE ELECTRICAL CHARACTERISTICS (VIN = 5V, TA = 25°C, unless otherwise specified.) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SCL, SDA Input Low VIO = 1.8V 0.58 V SCL, SDA Input High VIO = 1.8V 1.22 V SDA Leakage Current SDA=5V 1 µA SDA Output Low IOL = 5mA 0.35 V SCL Clock Frequency, fSCL 1000 kHz SCL Low Period, tLOW 0.5 µs SCL High Period, tHIGH 0.26 µs SDA Data Setup Time, tSU 50 ns SDA Data Hold Time, tHD (Note 1) 0 ns Start Setup Time, tST For Start Condition 260 ns Stop Setup Time, tSP For Stop Condition 260 ns Capacitance on SCL or SDA Pin 10 pF SDA Rise Time SDA, Tr Device requirement 120 ns SDA Fall Time SDA, Tf Device requirement 120 ns Note 1: Comply with I2C timings for 1MHz operation - “Fast Mode Plus”. Note 2: No internal timeout for I2C operations, however, I2C communication state machine will be reset when entering UV/POR State. Note 3: This is an I2C system specification only. Rise and fall time of SCL & SDA not controlled by the device. Note 4: Device Address is factory configurable to 7’h1A, 7’h3A, 7’h5A. Figure 2: I2C Data Transfer SDA SCL tST tSU tHD tSP tSCL Start condition Stop condition |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |