AX88772 datasheet(7/43 Pages) ASIX

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ASIX ELECTRONICS CORPORATION

AX88772

USB to 10/100 Fast Ethernet/HomePNA Controller

CRS

115

Carrier Sense. CRS is asserted high asynchronously by the PHY when

either transmit or receive medium is non-idle.

TX_CLK

102

Transmit Clock. TX_CLK is received from PHY to provide timing

reference for the transfer of TXD [3:0], TX_EN and TX_ER signals

on transmit direction of MII interface.

TXD [3:0]

82, 83, 84,

Transmit Data. TXD [3:0] is transitioned synchronously with respect

to the rising edge of TX_CLK.

TX_EN

Transmit Enable. TX_EN is transitioned synchronously with respect

to the rising edge of TX_CLK. TX_EN is asserted high to indicate a

valid TXD [3:0].

TX_ER

Transmit Coding Error. TX_ER is transitioned synchronously with

respect to the rising edge of TX_CLK. When asserted high for one or

more TX_CLK, the PHY shall emit one or more code-groups that are

not part of the valid data or delimiter set somewhere in the frame

being transmitted.

Serial EEPROM Interface

EECK

EEPROM Clock. EECK is an output clock to EEPROM to provide

timing reference for the transfer of EECS, EEDI, and EEDO signals.

EECS

EEPROM Chip Select. EECS is asserted high synchronously with

respect to rising edge of EECK as chip select signal.

EEDI

EEPROM Data In. EEDI is the serial output data to EEPROM’s data

input pin and is synchronous with respect to the rising edge of EECK.

EEDO

I5/PD

EEPROM Data Out. EEDO is the serial input data from EEPROM’s

data output pin.

Ethernet Phy Interface

XIN25M

25Mhz crystal or oscillator clock input. This clock is needed for the

embedded 10/100 Ethernet PHY to operate. The recommended

reference frequency is 25Mhz +/-0.005%.

This input pin is only 2.5V tolerant and should not apply 3.3V clock

signal directly to this pin if an external oscillator is used.

XOUT25M

25Mhz crystal or oscillator clock output. This output pin is 2.5V

tolerant.

RSTPB

Reset input of embedded Ethernet PHY: RSTPB is an active low input

used for resetting internal Ethernet PHY. When internal Ethernet

PHY is used, user can connect this pin to an external RC circuit,

which gets pulled-up to AVDDK (2.5V). The reset period from 50ms

to 150ms is recommended.

RXIP

Receive data input positive pin for both 10BASE-T and

100BASE-TX.

RXIN

Receive data input negative pin for both 10BASE-T and

100BASE-TX.

TXOP

Transmit data output positive pin for both 10BASE-T and 100

BASE-TX

TXON

Transmit data output negative pin for both 10BASE-T and 100

BASE-TX

IBREF

For Ethernet PHY’s internal biasing. Please connect to GND through

a 12.3Kohm resistor.

RX_LED

Receive activity LED indicator. This pin drives low and high in turn

(blinking) when Ethernet PHY is receiving and drives high when not

receiving.

COL_LED

Collision detected LED indicator. This pin drives low when the

Ethernet PHY detects collision and drives high when no collision.

LINK_LED

Link status LED indicator. This pin drives low continuously when the

Ethernet link is up and drives low and high in turn (blinking) when

Ethernet PHY is in receiving or transmitting state.

FDX_LED

Full-Duplex LED indicator. This pin drives low when the Ethernet

PHY is in full-duplex mode and drives high when in half duplex

mode.

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