AX88180 datasheet(21/47 Pages) ASIX

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AX88180

ASIX ELECTRONICS CORPORATION

4.12 RXCURT--RX Current Pointer Register

Offset Address = 0xFC34

Default = 0x0000_0000

Field

Name

Type

Default

Description

31:11

All 0’s

Reserved

10:0

RXCURPTR

R/W

All 0’s

RX Line Current Pointer.

Point to the last line that will be written by hardware. The unit of line is 16

bytes. AX88180 will maintain this register.

4.13 RXBOUND--RX Boundary Pointer Register

Offset Address = 0xFC38

Default = 0x0000_07FF

Field

Name

Type

Default

Description

31:11

All 0’s

Reserved

10:0

RXBUNPTR

R/W

0x7FF

RX Line Boundary Pointer.

Point to the last line that has been read by driver. The unit of line is 16

bytes.

When driver finished reading packet from RX buffer, it must update this

field.

4.14 MAC_CFG0--MAC Configuration0 Register

Offset Address = 0xFC40

Default = 0x0000_8157

Field

Name

Type

Default

Description

31:16

All 0’s

Reserved

SPEED100

R/W

Line Speed Mode

When this bit is enabled and bit12 of MAC_CFG1 is disabled, MAC will

operate in 100Mbps mode otherwise it operates in 10Mbps speed. If bit12

of MAC_CFG1 is enabled, this bit will be ignored

R/W

Reserved, this bit must set to 0 for normal operation

R/W

Reserved, this bit must set to 0 for normal operation.

RXFLOW

R/W

RX Flow Control

If this bit and bit8 of RX_CFG are enabled, MAC will perform flow

control and send pause on/off frame when the available space of receive

buffer is less than the value of RXBTHD0.

1 = enable

0 = disable

R/W

Reserved, this bit must set to 0 for normal operation.

10:4

IPG100

R/W

0x15

Inter Packet Gap (IPG) for 10/100M

This field defines the back-to-back transmit packet gap for 10/100M.

3:0

IPG1000

R/W

0x7

Inter Packet Gap for 1000M

This field defines the back-to-back transmit packet gap for 1000M only.

4.15 MAC_CFG1--MAC Configuration1 Register

Offset Address = 0xFC44

Default = 0x0000_6000

Field

Name

Type

Default

Description

31:15

All 0’s

Reserved

PUSRULE

R/W

Pause Frame Check Rule

When this bit is set, AX88180 accepts pause frame that DA can be any

value.

1 = don’t check DA field.

0 = check DA is equal to “01 80 C2 00 00 01”

CRCCHK

R/W

Check CRC of received Packet.

When this bit is enabled, AX88180 will drop any CRC error packet.

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