Data Sheet

ADP1762

Rev. D | Page 13 of 19

APPLICATIONS INFORMATION

CAPACITOR SELECTION

Output Capacitor

The ADP1762 is designed for operation with small, space-saving

ceramic capacitors, but it can function with most commonly

used capacitors as long as care is taken with the effective series

resistance (ESR) value. The ESR of the output capacitor affects

the stability of the LDO control loop. A minimum of 10 μF

capacitance with an ESR of 500 mΩ or less is recommended to

ensure the stability of the ADP1762. Transient response to changes

in load current is also affected by output capacitance. Using a

larger value of output capacitance improves the transient response

of the ADP1762 to large changes in load current. Figure 31 and

Figure 32 show the transient responses for output capacitance

values of 10 μF and 47 μF, respectively.

B

W

CH1 50.0mV

CH2 1.00A

M1.00µs

A CH2

640mA

1

2

T 18.70%

ILOAD

VOUT

Figure 31. Output Transient Response, COUT = 10 μF

CH1 50.0mV

CH2 1.00A

M1.00µs

A CH2

640mA

1

2

T 19.00%

ILOAD

VIN

Figure 32. Output Transient Response, COUT = 47 μF

Input Bypass Capacitor

Connecting a 10 μF capacitor from the VIN pin to the GND pin to

ground reduces the circuit sensitivity to the PCB layout, especially

when long input traces or high source impedance are encountered.

If output capacitance greater than 10 μF is required, it is

recommended that the input capacitor be increased to match it.

Input and Output Capacitor Properties

Use any good quality ceramic capacitors with the ADP1762, as

long as they meet the minimum capacitance and maximum

ESR requirements. Ceramic capacitors are manufactured with a

variety of dielectrics, each with different behavior over temperature

and applied voltage. Capacitors must have a dielectric adequate to

ensure the minimum capacitance over the necessary temperature

range and dc bias conditions. X5R or X7R dielectrics with a

voltage rating of 6.3 V or 10 V are recommended. Y5V and

Z5U dielectrics are not recommended, due to poor temperature

and dc bias characteristics.

Figure 33 shows the capacitance vs. bias voltage characteristics

of an 0805 case, 10 μF, 10 V, X5R capacitor. The voltage stability of

a capacitor is strongly influenced by the capacitor size and voltage

rating. In general, a capacitor in a larger package or with a higher

voltage rating exhibits better stability. The temperature variation

of the X5R dielectric is about ±15% over the −40°C to +85°C

temperature range and is not a function of package size or

voltage rating.

0

2

4

6

8

10

12

01

234

56

DC BIAS VOLTAGE (V)

Figure 33. Capacitance vs. DC Bias Voltage

Use Equation 4 to determine the worst case capacitance,

accounting for capacitor variation over temperature, component

tolerance, and voltage.

CEFF = COUT × (1 − Tempco) × (1 − TOL)

(4)

where:

CEFF is the effective capacitance at the operating voltage.

COUT is the output capacitor.

Tempco is the worst case capacitor temperature coefficient.

TOL is the worst case component tolerance.

In this example, the worst case temperature coefficient (tempco)

over −40°C to +85°C is assumed to be 15% for an X5R dielectric.

The tolerance of the capacitor (TOL) is assumed to be 10%, and

COUT = 10 μF at 1.0 V, as shown in Figure 33.