Data Sheet

ADP1762

Rev. D | Page 11 of 19

THEORY OF OPERATION

The ADP1762 is an LDO, low noise linear regulator that uses an

advanced proprietary architecture to achieve high efficiency

regulation. It also provides high PSRR and excellent line and load

transient response using a small 10 F ceramic output capacitor.

The device operates from a 1.10 V to 1.98 V input rail to provide

up to 2 A of output current. Supply current in shutdown mode

is 2 μA.

SS BLOCK

REFCAP

SS

PG

SHORT-CIRCUIT,

THERMAL

PROTECTION

INTERNAL

BIAS SUPPLY

ADP1762

VIN

VREG

EN

GND

REFERENCE,

BIAS

VOUT

SENSE

Figure 23. Functional Block Diagram, Fixed Output

SS BLOCK

SHORT-CIRCUIT,

THERMAL

PROTECTION

INTERNAL

BIAS SUPPLY

REFCAP

SS

PG

VIN

VREG

VADJ

IADJ

EN

GND

VOUT

SENSE

ADP1762

3×

Figure 24. Functional Block Diagram, Adjustable Output

Internally, the ADP1762 consists of a reference, an error amplifier,

and a pass device. The output current is delivered via the pass

device, which is controlled by the error amplifier, forming a

negative feedback system that ideally drives the feedback

voltage to equal the reference voltage. If the feedback voltage is

lower than the reference voltage, the negative feedback drives

more current, increasing the output voltage. If the feedback

voltage is higher than the reference voltage, the negative feedback

drives less current, decreasing the output voltage.

The ADP1762 is available in output voltages ranging from 0.9 V to

1.5 V for a fixed output. Contact a local Analog Devices, Inc., sales

representative for other fixed voltage options. The adjustable

output option can be set from 0.5 V to 1.5 V.

The ADP1762 uses the EN pin to enable and disable the VOUT

pin under normal operating conditions. When EN is high, VOUT

turns on. When EN is low, VOUT turns off. For automatic

startup, tie EN to VIN.

SOFT START FUNCTION

For applications that require a controlled startup, the ADP1762

provides a programmable soft start function. The programmable

soft start is useful for reducing inrush current upon startup and

for providing voltage sequencing. To implement soft start, connect

a small ceramic capacitor from SS to ground. At startup, a 10 μA

current source charges this capacitor. The voltage at SS limits the

ADP1762 start-up output voltage, providing a smooth ramp-up

to the nominal output voltage. To calculate the start-up time for

the fixed output and adjustable output, use the following equations:

tSTART-UP_FIXED = tDELAY + VREF × (CSS/ISS)

(1)

tSTART-UP_ADJ = tDELAY + VADJ × (CSS/ISS)

(2)

where:

tDELAY is a fixed delay of 100 μs.

VREF is a 0.5 V internal reference for the fixed output model option.

CSS is the soft start capacitance from SS to GND.

ISS is the current sourced from SS (10 μA).

VADJ is the voltage at the VADJ pin equal to RADJ × IADJ.

–0.1

0.1

0.3

0.5

0.7

0.9

1.1

1.3

1.5

1.7

–0.2

0.3

0.8

1.3

1.8

TIME (ms)

EN

CSS = 0nF

CSS = 10nF

CSS = 22nF

Figure 25. Fixed VOUT Ramp-Up with External Soft Start Capacitor (VOUT,EN) vs. Time

–0.5

0

0.5

1.0

1.5

2.0

–0.2

0.3

0.8

1.3

1.8

TIME (ms)

EN

VOUT = 0.5V; CSS = 10nF

VOUT = 0.5V; CSS = 22nF

VOUT = 1.5V; CSS = 10nF

VOUT = 1.5V; CSS = 22nF

Figure 26. Adjustable VOUT Ramp-Up with External Soft Start

Capacitor (VOUT, EN) vs. Time