Data Sheet

ADPL42002

analog.com

Rev. 1

17 of 22

Noise Reduction of the ADPL42002 in Adjustable Mode

The ultralow output noise of the ADPL42002 is achieved by keeping the LDO error amplifier in unity gain and setting

the reference voltage equal to the output voltage. This architecture does not work for an adjustable output voltage

LDO in the conventional sense. However, the ADPL42002 architecture allows any fixed output voltage to be set to a

higher voltage with an external voltage divider. For example, a fixed 5V output can be set to a 10V output according

to Equation 3 (see Figure 32):

VOUT = 5 V(1 + R1/R2)

(8)

The disadvantage of using the ADPL42002 in this manner is that the output voltage noise is proportional to the

output voltage. Therefore, it is best to choose a fixed output voltage that is close to the target voltage to minimize

the increase in output noise.

The adjustable LDO circuit can be modified to reduce the output voltage noise to levels close to that of the fixed

output ADPL42002. The circuit shown in Figure 32 adds two additional components to the output voltage setting

resistor divider. CNR and RNR are added in parallel with R1 to reduce the AC gain of the error amplifier. RNR is chosen

to be small with respect to R2. If RNR is 1% to 10% of the value of R2, the minimum AC gain of the error amplifier is

approximately 0.1dB to 0.8dB. The actual gain is determined by the parallel combination of RNR and R1. This gain

ensures that the error amplifier always operates at slightly greater than unity gain.

CNR is chosen by setting the reactance of CNR equal to R1 − RNR at a frequency between 1Hz and 50Hz. This setting

places the frequency where the AC gain of the error amplifier is 3dB down from the DC gain.

Figure 32. Noise Reduction Modification

Effect of Noise Reduction on Start-Up Time

The start-up time of the ADPL42002 is affected by the noise reduction network and must be considered in

applications where power supply sequencing is critical.

The noise reduction circuit adds a pole in the feedback loop, slowing down the start-up time. To approximate the

start-up time for an adjustable model with a noise reduction network using the following equation:

SSNRTIME (sec) = 5.5 × CNR × (RNR + RFB1)

(9)

For a CNR, RNR, and R1 combination of 1µF, 10kΩ, and 100kΩ, as shown in Figure 32, the start-up time is approximately

0.6sec. When SSNRTIME is greater than SSTIME, SSNRTIME dictates the length of the start-up time instead of the soft-start

capacitor.

VIN = 12V

100kΩ

200kΩ

CIN

2.2µF

ON

OFF

+

VOUT = 10V

COUT

2.2µF

RNR

10kΩ

R2

100kΩ

+

R1

100kΩ

CNR

1µF

+

CSS

1nF

VOUT

SENSE/ADJ

VIN

ADPL42002

GND

EN

SS