Data Sheet

ADRF6780S-CSL

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. A | 10 of 13

Figure 2. Pin Configuration

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

VDET

RF Detector Output. The voltage output is proportional to the decibel RF output power. The detector slope is nominally 50 mV/dB.

2

VPDT

Power Supply Connection for the RF Detector. Decouple the VPDT pin with 100 pF and 0.1 µF capacitors as close as possible to the

pin. Note that this pin must always be supplied with 5 V.

3, 9

VPRF

Power Supply Connections for the RF Path. Decouple the VPRF pins with 100 pF and 0.1 µF capacitors as close as possible to the

pins.

4, 6, 8, 19, 29

AGND

Analog Grounds. Connect these pins to a low impedance ground plane.

5, 7

RFOP, RFON

RF Outputs. These outputs are 100 Ω differential outputs for the RF path. Frequency range is 5.9 GHz to 23.6 GHz.

10

VATT

Modulator Output Attenuator Control Input. The RF voltage variable attenuator is controlled by applying a 0 V to 2.6 V control voltage

to the VATT pin. Increase the gain when the VATT voltage increases. This pin is linear in dB over the central gain range.

11 to 14

BBQN, BBQP,

BBIP, BBIN

I Channel and Q Channel Baseband Inputs. These inputs are high input impedance and are typically differentially terminated to a 100

Ω resistor using an off chip termination. The nominal common-mode bias level on these pins must be 0.5 V.

15

VPBB

Power Supply Connection for Baseband Path. Decouple the VPBB pin with 100 pF and 0.1 µF capacitors as close as possible to the

pin.

16

PWDN

Power Down. The ADRF6780S-CSL powers up when the PWDN pin is at a low logic level (<0.5 V). To power down the

ADRF6780S-CSL, apply a logic high level (>1.2 V). When the ADRF6780S-CSL is powered up, the SPI can also be used as a

power-down capability. The PWDN pin has an internal 18 kΩ pull-down resistor.

17

RST

Reset. This pin provides the ability to reset the SPI to the default register settings. Pull the RST pin to a logic high level in normal

operation. Driving the RST pin to a logic low level loads the default SPI register settings. The RST pin has an internal 7.75 kΩ pull-up

resistor.

18, 20

IFIN, IFIP

IF Inputs. These inputs are 100 Ω differential inputs for IF upconversion, and these pins must be AC-coupled.

When the IF mode is set, remove the 0 Ω R10 to R13 resistors from the I/Q lines.

21

VPBI

Power Supply Connection. Decouple the VPBI pin with 100 pF and 0.1 µF capacitors as close as possible to the pin.

22

VP18

1.8 V Power Supply. Decouple the VP18 pin with 100 pF and 0.1 µF capacitors as close as possible to the pin.

23

SDIN

Serial Data Input. Serial data applied to the SDIN pin is loaded into the SPI register upon a successful write command as indicated in

the timing diagrams (see the ADRF6780 data sheet for more details). The first MSB is a control bit, and this bit determines whether

data is written to the register (logic low) or read from the serial data output pin (logic high). The SDIN pin has an internal 18 kΩ

pull-down resistor.

24

SCLK

Serial Clock. This pin is the clock input for the SPI. The SCLK pin has an internal 18 kΩ pull-down resistor.

25

SDTO

Serial Data Output. The SDTO pin provides a SPI readback capability. See the timing diagrams for normal operation (see the

ADRF6780 data sheet for more details). The SDTO pin has an internal 18 kΩ pull-down resistor.

26

SEN

Serial Enable. When the SEN input pin goes high, the data stored in the shift registers is loaded into the register. The pin has an

internal 7.75 kΩ pull-up resistor.

27, 31

VPLO

Power Supply Connections for the LO Path. Decouple the VPLO pin with 100 pF and 0.1 µF capacitors as close as possible to the

pins.