TC9256, 57APG/AFG

2006-07-14

21

Note:

The asterisk “(*)” indicates an error state of over 180° phase difference relative to the reference

frequency.

2.

Phase Error Detection Bits (PE1to PE3)

The unlock bit detects, using the reference frequency cycle, the phase difference between the reference

frequency and the divided output of the programmable counter. The phase error detection bits (bits PE1to

PE3) are capable of precise phase error detection of

±0.55 to ±7.15 µs using the reference frequency cycle.

(If the UNLOCK bit is set to “1” and the phase difference relative to the reference frequency is over 180°,

bits PE1 to PE3 cannot correctly detect the phase error. Therefore, bits PE1to PE3 are normally used when

the UNLOCK bit is set to “0”.) Bits PE1to PE3 detects phase error normally when the phase difference is

−180°to 180° relative to the reference frequency cycle.

The phase error data can be read from the output register (D3H) as serial data PE1 to PE3.