SCL

SDA

t

(LOW)

t

R

t

F

t

(HDSTA)

t

(HDSTA)

t

(HDDAT)

t

(BUF)

t

(SUDAT)

t

(HIGH)

t

(SUSTA)

t

(SUSTO)

P

S

S

P

AMC80

SBOS559B – MAY 2011 – REVISED OCTOBER 2015

www.ti.com

6.6 Timing Requirements

At TA –40°C to +125°C and VS = 3V to 5.5V, unless otherwise noted.

FAST MODE(1)

HIGH-SPEED MODE(1)

MIN

MAX

MIN

MAX

UNIT

f(SCL)

SCL operating frequency

10

400

10

3400

kHz

t(BUF)

Bus free time between STOP and START conditions

600

160

ns

Hold time after repeated START condition. After this

t(HDSTA)

600

160

ns

period, the first clock is generated.

t(SUSTA)

Repeated START condition setup time

600

160

ns

t(SUSTO)

STOP condition setup time

600

160

ns

t(HDDAT)

Data hold time

0(2)

0(3)

ns

t(SUDAT)

Data setup time

100

10

ns

t(LOW)

Clock low period

1300

160

ns

t(HIGH)

Clock high period

600

60

ns

tR

Clock/Data input rise time

300

160

ns

tF

Clock/Data input fall time

300

160

ns

(1)

Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not specified and not

production tested.

(2)

For cases when the fall time of SCL is less than 20 ns and/or the rise time or fall time of SDA is less than 20 ns, the hold time should be

greater than 20 ns.

(3)

For cases when the fall time of SCL is less than 10 ns and/or the rise or fall time of SDA is less than 10 ns, the hold time should be

greater than 10 ns.

Figure 1. Serial Bus Interface Timing

8

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