PIC16LF18323-ESLASHPQTP datasheet(87/442 Pages) MICROCHIP

87 / 442 page

 2015 Microchip Technology Inc.

Preliminary

DS40001799A-page 87

PIC16(L)F18313/18323

7.6

INTCON: INTERRUPT CONTROL REGISTER

R/W-0/0

U-0

R-1/1

GIE

PEIE

—

—INTEDG

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

GIE:

Global Interrupt Enable bit

= Enables all active interrupts

= Disables all interrupts

bit 6

PEIE:

Peripheral Interrupt Enable bit

= Enables all active peripheral interrupts

= Disables all peripheral interrupts

bit 5-1

Unimplemented:

Read as ‘0’

bit 0

INTEDG:

Interrupt Edge Select bit

= Interrupt on rising edge of INT pin

= Interrupt on falling edge of INT pin

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User

software

should

ensure

the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

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