CDC2510C

3.3V PHASELOCK LOOP CLOCK DRIVER

SCAS621A − DECEMBER 1998 − REVISED DECEMBER 2004

8

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 5

PHASE ERROR

vs

CLOCK FREQUENCY

20

40

60

80

100

120

140

160

fc − Clock Frequency − MHz

−100

−150

−250

−300

−350

−400

−200

−50

0

−450

−500

VCC = 3.3 V

C(LY) = 30 pF

C(LF) = 0

TA = 25°C

See Note A

Figure 6

PHASE ERROR

vs

SUPPLY VOLTAGE

−100

−150

−250

−300

−350

−400

−200

3.1

3.2

3.3

3.4

3.5

−50

0

−450

−500

fc = 100 MHz

C(LY) = 30 pF

C(LF) = 0

TA = 25°C

See Note A

VCC − Supply Voltage − V

Figure 7

−300

−400

−500

−700

35

45

55

65

75

85

95

105

115

125

−600

−200

VCC = 3.3 V

C(LY) = C(LF) = 30 pF

TA = 25°C

See Notes B to D

fc − Clock Frequency − MHz

CDC2510C

STATIC PHASE ERROR

vs

CLOCK FREQUENCY

Figure 8

−300

−400

−500

−700

35

45

55

65

75

85

95

105

115

125

−600

−200

VCC = 3.3 V

C(LY) = C(LF) = 30 pF

See Notes B to D

fc − Clock Frequency − MHz

CDC2510A

STATIC PHASE ERROR

vs

CLOCK FREQUENCY

NOTES: A. Trace feedback length FBOUT to FBIN = 5 mm, ZO = 50 Ω

B. Phase error measured from CLK to FBIN

C. CLY = Lumped capacitive load at Y

D. CLF = Lumped feedback capacitance at FBIN