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MCP3425 数据表(PDF) 16 Page - Microchip Technology |
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MCP3425 数据表(HTML) 16 Page - Microchip Technology |
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16 / 30 page  MCP3425 DS22072A-page 16 © 2007 Microchip Technology Inc. 5.5 High-Speed (HS) Mode The I2C specification requires that a high-speed mode device must be ‘activated’ to operate in high-speed mode. This is done by sending a special address byte of 00001XXX following the START bit. The XXX bits are unique to the High-Speed (HS) mode Master. This byte is referred to as the High-Speed (HS) Master Mode Code (HSMMC). The MCP3425 device does not acknowledge this byte. However, upon receiving this code, the MCP3425 switches on its HS mode filters and communicates up to 3.4 MHz on SDA and SCL. The device will switch out of the HS mode on the next STOP condition. For more information on the HS mode, or other I2C modes, please refer to the Phillips I2C specification. 5.6 I2C Bus Characteristics The I2C specification defines the following bus protocol: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined using Figure 5-5. 5.6.1 BUS NOT BUSY (A) Both data and clock lines remain HIGH. 5.6.2 START DATA TRANSFER (B) A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition. 5.6.3 STOP DATA TRANSFER (C) A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations can be ended with a STOP condition. 5.6.4 DATA VALID (D) The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. 5.6.5 ACKNOWLEDGE The Master (microcontroller) and the slave (MCP3425) use an acknowledge pulse as a hand shake of communication for each byte. The ninth clock pulse of each byte is used for the acknowledgement. The acknowledgement is achieved by pulling-down the SDA line “LOW” during the 9th clock pulse. The clock pulse is always provided by the Master (microcontrol- ler) and the acknowledgement is issued by the receiving device of the byte (Note: The transmitting device must release the SDA line (“HIGH”) during the acknowledge pulse.). For example, the slave (MCP3425) issues the acknowledgement (bring down the SDA line “LOW”) after the end of each receiving byte, and the master (microcontroller) issues the acknowledgement when it reads data from the Slave (MCP3425). When the MCP3425 is addressed, it generates an acknowledge after receiving each byte successfully. The Master device (microcontroller) must provide an extra clock pulse (9th pulse of each byte) for the acknowledgement from the MCP3425 (slave). The MCP3425 (slave) pulls-down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge clock pulse. During reads, the Master (microcontroller) can terminate the current read operation by not providing an acknowledge bit on the last byte that has been clocked out from the MCP3425. In this case, the MCP3425 releases the SDA line to allow the master (microcontroller) to generate a STOP or repeated START condition. FIGURE 5-5: Data Transfer Sequence on the Serial Bus. SCL SDA (A) (B) (D) (D) (A) (C) START CONDITION ADDRESS OR ACKNOWLEDGE VALID DATA ALLOWED TO CHANGE STOP CONDITION |
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