MCP604-IP datasheet(13/34 Pages) MICROCHIP

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DS21314G-page 13

MCP601/1R/2/3/4

4.2

Rail-to-Rail Output

There are two specifications that describe the output

swing capability of the MCP601/1R/2/3/4 family of op

amps. The first specification (Maximum Output Voltage

Swing) defines the absolute maximum swing that can

be achieved under the specified load conditions. For

instance, the output voltage swings to within 15 mV of

the negative rail with a 25 k

Ω load to V

DD/2. Figure 2-33

shows how the output voltage is limited when the input

goes beyond the linear region of operation.

The second specification that describes the output

swing capability of these amplifiers is the Linear Output

Voltage Swing. This specification defines the maximum

output swing that can be achieved while the amplifier is

still operating in its linear region. To verify linear

operation in this range, the large signal (DC Open-Loop

Gain (AOL)) is measured at points 100 mV inside the

supply rails. The measurement must exceed the

specified gains in the specification table.

4.3

MCP603 Chip Select

The MCP603 is a single amplifier with Chip Select

(CS). When CS is pulled high, the supply current drops

to -0.7 µA (typ.), which is pulled through the CS pin to

VSS. When this happens, the amplifier output is put into

a high-impedance state. Pulling CS low enables the

amplifier.

The CS pin has an internal 5 M

Ω (typical) pull-down

resistor connected to VSS, so it will go low if the CS pin

is left floating. Figure 1-1 is the Chip Select timing

diagram and shows the output voltage, supply currents,

and CS current in response to a CS pulse. Figure 2-27

shows the measured output voltage response to a CS

pulse.

4.4

Capacitive Loads

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response with overshoot and ringing in the step

response.

When driving large capacitive loads with these op

amps (e.g., > 40 pF when G = +1), a small series

resistor at the output (RISO in Figure 4-4) improves the

feedback loop’s phase margin (stability) by making the

output load resistive at higher frequencies. The

bandwidth will be generally lower than the bandwidth

with no capacitive load.

FIGURE 4-4:

Output resistor RISO

stabilizes large capacitive loads.

Figure 4-5 gives recommended RISO values for

different capacitive loads and gains. The x-axis is the

normalized load capacitance (CL/GN) in order to make

it easier to interpret the plot for arbitrary gains. GN is the

circuit’s noise gain. For non-inverting gains, GN and the

gain are equal. For inverting gains, GN = 1 + |Gain|

(e.g., -1 V/V gives GN = +2 V/V).

FIGURE 4-5:

Recommended RISO values

for capacitive loads.

Once you have selected RISO for your circuit, double-

check the resulting frequency response peaking and

step response overshoot in your circuit. Evaluation on

the bench and simulations with the MCP601/1R/2/3/4

SPICE macro model are very helpful. Modify RISO’s

value until the response is reasonable.

4.5

Supply Bypass

With this family of op amps, the power supply pin (VDD

for single-supply) should have a local bypass capacitor

(i.e., 0.01 µF to 0.1 µF) within 2 mm for good high-

frequency performance. It also needs a bulk capacitor

(i.e., 1 µF or larger) within 100 mm to provide large,

slow currents. This bulk capacitor can be shared with

nearby analog parts.

MCP60X

RISO

VOUT

–

Normalized Load Capacitance;

CL / GN (F)

10p

100p

10n

100

GN = +1

GN ≥ +2

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