数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

MP8712GL 数据表(PDF) 21 Page - Monolithic Power Systems

部件名 MP8712GL
功能描述  High-Efficiency, 12A, 3V to 18V, Synchronous Step-Down Converter with Power Good, External Soft Start and OVP
PDF  27 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  MPS [Monolithic Power Systems]
网页  http://www.monolithicpower.com
标志 MPS - Monolithic Power Systems

MP8712GL 数据表(HTML) 21 Page - Monolithic Power Systems

Back Button MP8712GL Datasheet HTML 17Page - Monolithic Power Systems MP8712GL Datasheet HTML 18Page - Monolithic Power Systems MP8712GL Datasheet HTML 19Page - Monolithic Power Systems MP8712GL Datasheet HTML 20Page - Monolithic Power Systems MP8712GL Datasheet HTML 21Page - Monolithic Power Systems MP8712GL Datasheet HTML 22Page - Monolithic Power Systems MP8712GL Datasheet HTML 23Page - Monolithic Power Systems MP8712GL Datasheet HTML 24Page - Monolithic Power Systems MP8712GL Datasheet HTML 25Page - Monolithic Power Systems Next Button
Zoom Inzoom in Zoom Outzoom out
 21 / 27 page
background image
MP8712 – 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
MP8712 Rev. 1.2
MonolithicPower.com
21
3/19/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2021 MPS. All Rights Reserved.
PCB Layout Guidelines (8)
Efficient PCB layout is critical for stable
operation. A four-layer layout is strongly
recommended
to
achieve
better
thermal
performance. For best results, refer to Figure 7
and follow the guidelines below.
1. Place the high current paths (PGND, VIN,
and SW) very close to the device with short,
direct, and wide traces.
2. Keep the VIN and PGND pads connected
with large coppers.
3. Use at least two layers for the VIN and
PGND trace to achieve better thermal
performance.
4. Add several vias close to the VIN and
PGND pads to help with thermal dissipation.
Place m than one via adjacent to the inner
edge of PGND pad which connects to
AGND pad through low impedance routing
or ground plane.
5. Place the input capacitors as close to VIN
and PGND as possible.
6. Place the decoupling capacitor as close to
VCC and AGND as possible.
7. Add several vias close the the AGND pad,
and connect to PGND plane with Kelvin
connection.
8. Place the external feedback resistors next
to FB.
9. Ensure that there is no via on the FB trace.
10. Keep the switching node (SW) short and
away from the feedback network.
11. Keep the BST voltage path (BST, C3, and
SW) as short as possible.
NOTE:
8)
The recommended layout is based on the Typical
Application Circuits on page 22 to page 25.
Figure 7: Recommended Layout
Design Example
Table 2 is a design example following the
application guidelines for the specifications.
Table 2: Design Example
VIN
12V, 3V
VOUT
1V
IOUT
12A
The detailed application schematics are shown
in Figure 8 through Figure 17. The typical
performance and circuit waveforms are shown
in the Typical Performance Characteristics
section. For more device applications, please
refer to the related evaluation board datasheets.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com