DA[9:0]

DB[9:0]

SLEEP

CLKA/B

WRTA/B

Internal

Digital In

DVDD

DGND

f − Frequency − MHz

−110

−90

−70

−50

−30

−10

19.0

19.5

20.0

20.5

21.0

21.5

22.0

fdata = 78 MSPS

fout1 = 20.1 MHz

fout2 = 21.1 MHz

Dual Bus Mode

G011

f − Frequency − MHz

−110

−90

−70

−50

−30

−10

29.0

29.5

30.0

30.5

31.0

31.5

32.0

fdata = 165 MSPS

fout1 = 30.1 MHz

fout2 = 31.1 MHz

Dual Bus Mode

G012

DAC5652-EP

www.ti.com

SGLS341C – JUNE 2006 – REVISED APRIL 2013

TYPICAL CHARACTERISTICS (continued)

TWO-TONE SPECTRUM

TWO-TONE SPECTRUM

Figure 12.

Figure 13.

DIGITAL INPUTS AND TIMING

Digital Inputs

The data input ports of the DAC5652 accept a standard positive coding with data bits DA9 and DB9 being the

most significant bits (MSBs). The converter outputs are specified to support a clock rate up to 200 MSPS. The

best performance is typically achieved with a symmetric duty cycle for write and clock; however, the duty cycle

may vary as long as the timing specifications are met. Similarly, the setup and hold times may be chosen within

their specified limits.

All digital inputs of the DAC5652 are CMOS compatible. Figure 14 and Figure 15 show schematics of the

equivalent CMOS digital inputs of the DAC5652. The 10-bit digital data input follows the offset positive binary

coding scheme. The DAC5652 is designed to operate with a digital supply (DVDD) of 3 V to 3.6 V.

Figure 14. CMOS/TTL Digital Equivalent Input With Internal Pulldown Resistor

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