Functional Description (Continued)

ternal interrupt will be issued Note that the linear power fail

circuitry is switched off automatically when using VBB in

standby mode

INITIAL POWER ON DETECT AND

POWER FAIL TIME SAVE

There are two other functions provided on the DP8573A to

ease power supply control These are an initial Power On

detect circuit which also can be used as a time keeping

failure detect and a time save on power failure

On initial power up the Oscillator Fail Flag will be set to a

one and the real time clock start bit reset to a zero This

indicates that an oscillator fail event has occurred and time

keeping has failed

The Oscillator Fail flag will not be reset until the real-time

clock is started This allows the system to discriminate be-

tween an initial power-up and recovery from a power failure

If the battery backed mode is selected then bit D6 of the

Periodic Flag Register must be written low This will not af-

fect the contents of the Oscillator Fail Flag

To relieve CPU overhead for saving time upon power failure

the Time Save Enable bit is provided to do this automatical-

ly (See also Reading the Clock Latched Read) The Time

Save Enable bit when set causes the Time Save RAM to

follow the contents of the clock This bit can be reset by

software but if set before a power failure occurs it will auto-

matically be reset when the clock switches to the battery

supply (not when a power failure is detected by the PFAIL

pin) Thus writing a one to the Time Save bit enables both a

software write or power fail write

SINGLE POWER SUPPLY APPLICATIONS

The DP8573A can be used in a single power supply applica-

tion To achieve this the VBB pin must be connected to

ground and the power connected to VCC The Oscillator

FailedSingle Supply bit in the Periodic Flag Register should

be set to a logic 1 which will disable the oscillator battery

reference circuit The power fail interrupt should also be dis-

abled This will turn off the linear power fail detection cir-

cuits and will eliminate any quiescent power drawn through

these circuits

DETAILED REGISTER DESCRIPTION

There are 5 external address bits Thus the host microproc-

essor has access to 28 locations at one time An internal

switching scheme provides a total of 30 locations

The only register that does not get switched is the Main

Status Register It contains the register select bit as well as

status information

A memory map is shown in

Figure 2 and register addressing

in Table III They show the name address and page loca-

tions for the DP8573A

TABLE III RegisterCounterRAM

Addressing for DP8573A

A0-4

RS

Description

(Note 1)

CONTROL REGISTERS

00

X

Main Status Register

01

0

NA

02

0

NA

03

0

Periodic Flag Register

04

0

Time Save Control Register

01

1

Real Time Mode Register

02

1

Output Mode Register

03

1

Interrupt Control Register 0

04

1

Interrupt Control Register 1

COUNTERS (CLOCK CALENDAR)

05

X

1100 110 Seconds

(0 – 99)

06

X

Seconds

(0 – 59)

07

X

Minutes

(0 – 59)

08

X

Hours

(1 – 12 0 – 23)

09

X

Days of Month

(1 – 28293031)

0A

X

Months

(1 – 12)

0B

X

Years

(0 – 99)

0C

X

RAM

0D

X

D0 D1 bits only

0E

X

Day of Week

(1 – 7)

0F

X

NA

10

X

NA

11

X

NA

12

X

NA

TIME COMPARE RAM

13

X

Sec Compare RAM

(0 – 59)

14

X

Min Compare RAM

(0 – 59)

15

X

Hours Compare RAM

(1 – 12 0 – 23)

16

X

DOM Compare RAM

(1 – 28293031)

17

X

Months Compare RAM (1 – 12)

18

X

DOW Compare RAM

(1 – 7)

TIME SAVE RAM

19

X

Seconds Time Save RAM

1A

X

Minutes Time Save RAM

1B

X

Hours Time Save RAM

1C

X

Day of Month Time Save RAM

1D

X

Months Time Save RAM

1E

1

RAM

1F

X

RAMTest Mode Register

Note 1

RSRegister Select (Bit D6 of Main Status Register)

10